source: firmware/FTM/test_firmware/FTM_test2/ftm_board_test2.ucf@ 10110

Last change on this file since 10110 was 10046, checked in by vogler, 14 years ago
Test firmware for FTM hardware testing
File size: 16.6 KB
Line 
1########################################################
2# FTM Board
3# FACT Trigger Master
4#
5# Pin location constraints
6#
7# by Patrick Vogler
8# 5 October 2010
9#
10# FTM Test 2: Trigger-Primitives and LVDS outputs
11########################################################
12
13
14#Clock
15#######################################################
16NET clk LOC = Y14 | IOSTANDARD=LVCMOS33; # FPGA-CLK from oscillator U47
17
18
19# Ethernet Interface
20# connection to the WIZnet W5300 ethernet controller (U37)
21# on IO-Bank 1
22#######################################################
23# data bus
24# NET W_D<0> LOC = M22 | IOSTANDARD=LVCMOS33; # 16-bit data bus to W5300
25# NET W_D<1> LOC = L22 | IOSTANDARD=LVCMOS33; #
26# NET W_D<2> LOC = K23 | IOSTANDARD=LVCMOS33; #
27# NET W_D<3> LOC = K25 | IOSTANDARD=LVCMOS33; #
28# NET W_D<4> LOC = K26 | IOSTANDARD=LVCMOS33; #
29# NET W_D<5> LOC = J22 | IOSTANDARD=LVCMOS33; #
30# NET W_D<6> LOC = J23 | IOSTANDARD=LVCMOS33; #
31# NET W_D<7> LOC = G23 | IOSTANDARD=LVCMOS33; #
32# NET W_D<8> LOC = G24 | IOSTANDARD=LVCMOS33; #
33# NET W_D<9> LOC = F24 | IOSTANDARD=LVCMOS33; #
34# NET W_D<10> LOC = F25 | IOSTANDARD=LVCMOS33; #
35# NET W_D<11> LOC = E24 | IOSTANDARD=LVCMOS33; #
36# NET W_D<12> LOC = E26 | IOSTANDARD=LVCMOS33; #
37# NET W_D<13> LOC = D24 | IOSTANDARD=LVCMOS33; #
38# NET W_D<14> LOC = D26 | IOSTANDARD=LVCMOS33; #
39# NET W_D<15> LOC = D25 | IOSTANDARD=LVCMOS33; #
40
41# W5300 address bus
42# NET W_A<1> LOC = AA25 | IOSTANDARD=LVCMOS33; # there is NO net W_A0 because
43# NET W_A<2> LOC = AA24 | IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode
44# NET W_A<3> LOC = AA23 | IOSTANDARD=LVCMOS33; # see W5300 datasheet
45# NET W_A<4> LOC = Y25 | IOSTANDARD=LVCMOS33; #
46# NET W_A<5> LOC = Y24 | IOSTANDARD=LVCMOS33; #
47# NET W_A<6> LOC = Y23 | IOSTANDARD=LVCMOS33; #
48# NET W_A<7> LOC = W23 | IOSTANDARD=LVCMOS33; #
49# NET W_A<8> LOC = V25 | IOSTANDARD=LVCMOS33; #
50# NET W_A<9> LOC = V24 | IOSTANDARD=LVCMOS33; #
51
52# W5300 controll signals
53# the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
54# W_CS is also routed to testpoint JP7
55# NET W_CS LOC = T20 | IOSTANDARD=LVCMOS33; # W5300 chip select
56# NET W_INT LOC = U22 | IOSTANDARD=LVCMOS33; # interrupt
57# NET W_RD LOC = R20 | IOSTANDARD=LVCMOS33; # read
58# NET W_WR LOC = P22 | IOSTANDARD=LVCMOS33; # write
59# NET W_RES LOC = U23 | IOSTANDARD=LVCMOS33; # reset W5300 chip
60
61# W5300 buffer ready indicator
62# NET W_BRDY<0> LOC = AB26 | IOSTANDARD=LVCMOS33; #
63# NET W_BRDY<1> LOC = AC26 | IOSTANDARD=LVCMOS33; #
64# NET W_BRDY<2> LOC = AC25 | IOSTANDARD=LVCMOS33; #
65# NET W_BRDY<3> LOC = AD26 | IOSTANDARD=LVCMOS33; #
66
67# W5300 associated testpoints
68# NET W_T<0> LOC = N21 | IOSTANDARD=LVCMOS33; #
69# NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; #
70# NET W_T<2> LOC = K21 | IOSTANDARD=LVCMOS33; #
71# NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; #
72
73
74# SPI Interface
75# connection to the EEPROM U36 (AL25L016M) and the temperature
76# sensors U45, U46, U48 and U49 (all MAX6662)
77# on IO-Bank 1
78#######################################################
79# NET S_CLK LOC = U20 | IOSTANDARD=LVCMOS33; # SPI clock
80
81# EEPROM
82# NET MOSI LOC = AA22 | IOSTANDARD=LVCMOS33; # master out slave in
83# NET MISO LOC = V22 | IOSTANDARD=LVCMOS33; # master in slave out
84# NET EE_CS LOC = G22 | IOSTANDARD=LVCMOS33; # master out slave in
85
86# temperature sensors
87# NET SIO LOC = F22 | IOSTANDARD=LVCMOS33; # serial IO
88# NET TS_CS<0> LOC = H21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select0
89# NET TS_CS<1> LOC = J21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select1
90# NET TS_CS<2> LOC = C25 | IOSTANDARD=LVCMOS33; # temperature sensors chip select2
91# NET TS_CS<3> LOC = C26 | IOSTANDARD=LVCMOS33; # temperature sensors chip select3
92
93
94# Trigger primitives inputs
95# on IO-Bank 2
96#######################################################
97# crate 0
98# crate A
99# NET Trig_Prim_A<0> LOC = AC6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0>
100# NET Trig_Prim_A<1> LOC = AD6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1>
101# NET Trig_Prim_A<2> LOC = AF3 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2>
102# NET Trig_Prim_A<3> LOC = AE4 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3>
103# NET Trig_Prim_A<4> LOC = AE6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4>
104# NET Trig_Prim_A<5> LOC = AE7 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5>
105# NET Trig_Prim_A<6> LOC = AE8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6>
106# NET Trig_Prim_A<7> LOC = AC8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7>
107# NET Trig_Prim_A<8> LOC = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8>
108# NET Trig_Prim_A<9> LOC = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9>
109
110# crate 1
111# crate B
112# NET Trig_Prim_B<0> LOC = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0>
113# NET Trig_Prim_B<1> LOC = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1>
114# NET Trig_Prim_B<2> LOC = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2>
115# NET Trig_Prim_B<3> LOC = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3>
116# NET Trig_Prim_B<4> LOC = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4>
117# NET Trig_Prim_B<5> LOC = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5>
118# NET Trig_Prim_B<6> LOC = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6>
119# NET Trig_Prim_B<7> LOC = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7>
120# NET Trig_Prim_B<8> LOC = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8>
121# NET Trig_Prim_B<9> LOC = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9>
122
123# crate 2
124# crate C
125# NET Trig_Prim_C<0> LOC = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0>
126# NET Trig_Prim_C<1> LOC = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1>
127# NET Trig_Prim_C<2> LOC = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2>
128# NET Trig_Prim_C<3> LOC = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3>
129# NET Trig_Prim_C<4> LOC = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4>
130# NET Trig_Prim_C<5> LOC = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5>
131# NET Trig_Prim_C<6> LOC = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6>
132# NET Trig_Prim_C<7> LOC = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7>
133# NET Trig_Prim_C<8> LOC = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8>
134# NET Trig_Prim_C<9> LOC = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9>
135
136# crate 3
137# crate D
138# NET Trig_Prim_D<0> LOC = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0>
139# NET Trig_Prim_D<1> LOC = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1>
140# NET Trig_Prim_D<2> LOC = AC9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2>
141# NET Trig_Prim_D<3> LOC = AB9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3>
142# NET Trig_Prim_D<4> LOC = AB7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4>
143# NET Trig_Prim_D<5> LOC = AF8 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5>
144# NET Trig_Prim_D<6> LOC = AF4 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6>
145# NET Trig_Prim_D<7> LOC = AF5 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7>
146# NET Trig_Prim_D<8> LOC = AD7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8>
147# NET Trig_Prim_D<9> LOC = AE3 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9>
148
149
150# NIM inputs
151#######################################################
152# on IO-Bank 3
153# NET ext_Trig<1> LOC = B1 | IOSTANDARD=LVCMOS33; #
154# NET ext_Trig<2> LOC = B2 | IOSTANDARD=LVCMOS33; #
155# NET Veto LOC = E4 | IOSTANDARD=LVCMOS33; #
156# NET NIM_In<0> LOC = D3 | IOSTANDARD=LVCMOS33; #
157# NET NIM_In<1> LOC = F4 | IOSTANDARD=LVCMOS33; #
158# NET NIM_In<2> LOC = E3 | IOSTANDARD=LVCMOS33; #
159
160# on IO-Bank 0
161# NET NIM_In3_GCLK LOC = K14 | IOSTANDARD=LVCMOS33; # input with global clock buffer
162 # available
163
164
165# LEDs
166# on IO-Banks 0 and 3
167#######################################################
168# red
169# NET LED_red<0> LOC = D6 | IOSTANDARD=LVCMOS33; # IO-Bank 0
170# NET LED_red<1> LOC = A4 | IOSTANDARD=LVCMOS33; # IO-Bank 0
171# NET LED_red<2> LOC = E1 | IOSTANDARD=LVCMOS33; # IO-Bank 3
172# NET LED_red<3> LOC = J5 | IOSTANDARD=LVCMOS33; # IO-Bank 3
173
174# yellow
175# NET LED_ye<0> LOC = C5 | IOSTANDARD=LVCMOS33; # IO-Bank 0
176# NET LED_ye<1> LOC = B3 | IOSTANDARD=LVCMOS33; # IO-Bank 0
177
178# green
179# NET LED_gn<0> LOC = B4 | IOSTANDARD=LVCMOS33; # IO-Bank 0
180# NET LED_gn<1> LOC = A3 | IOSTANDARD=LVCMOS33; # IO-Bank 0
181
182
183# Clock conditioner LMK03000
184# on IO-Bank 3
185#######################################################
186# NET CLK_Clk_Cond LOC = G4 | IOSTANDARD=LVCMOS33; # IO-Bank 3
187# NET LE_Clk_Cond LOC = F2 | IOSTANDARD=LVCMOS33; # IO-Bank 3
188# NET LD_Clk_Cond LOC = J4 | IOSTANDARD=LVCMOS33; # IO-Bank 3
189# NET DATA_Clk_Cond LOC = F3 | IOSTANDARD=LVCMOS33; # IO-Bank 3
190# NET SYNC_Clk_Cond LOC = H2 | IOSTANDARD=LVCMOS33; # IO-Bank 3
191
192
193# various RS-485 Interfaces
194# on IO-Bank 3
195#######################################################
196# Bus 1: FTU slow control
197# NET Bus1_Tx_En LOC = H1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
198# NET Bus1_Rx_En LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
199
200# crate 0
201# NET Bus1_RxD_0 LOC = K3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
202# NET Bus1_TxD_0 LOC = L3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
203
204# crate 1
205# NET Bus1_RxD_1 LOC = M2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
206# NET Bus1_TxD_1 LOC = N4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
207
208# crate 2
209# NET Bus1_RxD_2 LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
210# NET Bus1_TxD_2 LOC = P4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
211
212# crate 3
213# NET Bus1_RxD_3 LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
214# NET Bus1_TxD_3 LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
215
216
217# Bus 2: Trigger-ID to FAD boards
218# NET Bus2_Tx_En LOC = K2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
219# NET Bus2_Rx_En LOC = K4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
220
221# crate 0
222# NET Bus2_RxD_0 LOC = L4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
223# NET Bus2_TxD_0 LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
224
225# crate 1
226# NET Bus2_RxD_1 LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
227# NET Bus2_TxD_1 LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
228
229# crate 2
230# NET Bus2_RxD_2 LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
231# NET Bus2_TxD_2 LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
232
233# crate 3
234# NET Bus2_RxD_3 LOC = U4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
235# NET Bus2_TxD_3 LOC = U2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
236
237
238# auxiliary access
239# NET Aux_Rx_D LOC = W3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
240# NET Aux_Tx_D LOC = Y2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
241# NET Aux_Rx_En LOC = W4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable
242# NET Aux_Tx_En LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary
243 # Trigger-ID
244
245# auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
246# NET TrID_Rx_D LOC = U6 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
247# NET TrID_Tx_D LOC = T7 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
248
249
250# Crate-Resets
251# on IO-Bank 3
252#######################################################
253NET Crate_Res0 LOC = M1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
254NET Crate_Res1 LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
255NET Crate_Res2 LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
256NET Crate_Res3 LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
257
258
259# Busy signals from the FAD boards
260# on IO-Bank 3
261#######################################################
262# NET Busy0 LOC = M4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
263# NET Busy1 LOC = P2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
264# NET Busy2 LOC = R4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
265# NET Busy3 LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
266
267
268# NIM outputs
269# on IO-Bank 0
270# LVDS output at the FPGA followed by LVDS to NIM
271# conversion stage
272#######################################################
273# calibration
274NET Cal_NIM1_p LOC = D18 | IOSTANDARD=LVDS_33; # Cal_NIM1+
275NET Cal_NIM1_n LOC = C18 | IOSTANDARD=LVDS_33; # Cal_NIM1-
276NET Cal_NIM2_p LOC = B18 | IOSTANDARD=LVDS_33; # Cal_NIM2+
277NET Cal_NIM2_n LOC = A18 | IOSTANDARD=LVDS_33; # Cal_NIM2-
278
279# auxiliarry / spare NIM outputs
280NET NIM_Out0_p LOC = C17 | IOSTANDARD=LVDS_33; # NIM_Out0+
281NET NIM_Out0_n LOC = B17 | IOSTANDARD=LVDS_33; # NIM_Out0-
282NET NIM_Out1_p LOC = D17 | IOSTANDARD=LVDS_33; # NIM_Out1+
283NET NIM_Out1_n LOC = C16 | IOSTANDARD=LVDS_33; # NIM_Out1-
284
285
286# fast control signal outputs
287# LVDS output at the FPGA followed by LVDS to NIM
288# conversion stage
289#######################################################
290NET RES_p LOC = D16 | IOSTANDARD=LVDS_33; # RES+ Reset
291NET RES_n LOC = C15 | IOSTANDARD=LVDS_33; # RES- IO-Bank 0
292
293NET TRG_p LOC = B15 | IOSTANDARD=LVDS_33; # TRG+ Trigger
294NET TRG_n LOC = A15 | IOSTANDARD=LVDS_33; # TRG- IO-Bank 0
295
296NET TIM_Run_p LOC = AF25 | IOSTANDARD=LVDS_33; # TIM_Run+ Time Marker
297NET TIM_Run_n LOC = AE25 | IOSTANDARD=LVDS_33; # TIM_Run-
298 # on IO-Bank2
299NET TIM_Sel LOC = AD22 | IOSTANDARD=LVCMOS33; # Time Marker selector
300 # IO-Bank 2
301# NET CLD_FPGA LOC = AA14 | IOSTANDARD=LVCMOS33; # DRS-Clock feedback into FPGA
302
303
304# LVDS calibration outputs
305# on IO-Bank 0
306#######################################################
307# to connector J13
308NET Cal_0_p LOC = D22 | IOSTANDARD=LVDS_33; # Cal_0+
309NET Cal_0_n LOC = C22 | IOSTANDARD=LVDS_33; # Cal_0-
310NET Cal_1_p LOC = D23 | IOSTANDARD=LVDS_33; # Cal_1+
311NET Cal_1_n LOC = C23 | IOSTANDARD=LVDS_33; # Cal_1-
312NET Cal_2_p LOC = B23 | IOSTANDARD=LVDS_33; # Cal_2+
313NET Cal_2_n LOC = A22 | IOSTANDARD=LVDS_33; # Cal_2-
314NET Cal_3_p LOC = C21 | IOSTANDARD=LVDS_33; # Cal_3+
315NET Cal_3_n LOC = B21 | IOSTANDARD=LVDS_33; # Cal_3-
316
317# to connector J12
318NET Cal_4_p LOC = E21 | IOSTANDARD=LVDS_33; # Cal_4+
319NET Cal_4_n LOC = D21 | IOSTANDARD=LVDS_33; # Cal_4-
320NET Cal_5_p LOC = D20 | IOSTANDARD=LVDS_33; # Cal_5+
321NET Cal_5_n LOC = C20 | IOSTANDARD=LVDS_33; # Cal_5-
322NET Cal_6_p LOC = B20 | IOSTANDARD=LVDS_33; # Cal_6+
323NET Cal_6_n LOC = A20 | IOSTANDARD=LVDS_33; # Cal_6-
324NET Cal_7_p LOC = B19 | IOSTANDARD=LVDS_33; # Cal_7+
325NET Cal_7_n LOC = A19 | IOSTANDARD=LVDS_33; # Cal_7-
326
327
328# Testpoints
329######################################################
330# Connector T7
331# IO-Bank 0
332# NET TP<0> LOC = B14 | IOSTANDARD=LVCMOS33; #
333# NET TP<1> LOC = A14 | IOSTANDARD=LVCMOS33; #
334# NET TP<2> LOC = C13 | IOSTANDARD=LVCMOS33; #
335# NET TP<3> LOC = B13 | IOSTANDARD=LVCMOS33; #
336
337# Connector T10
338# IO-Bank 0
339# NET TP<4> LOC = D13 | IOSTANDARD=LVCMOS33; #
340# NET TP<5> LOC = C12 | IOSTANDARD=LVCMOS33; #
341# NET TP<6> LOC = B12 | IOSTANDARD=LVCMOS33; #
342# NET TP<7> LOC = A12 | IOSTANDARD=LVCMOS33; #
343
344# on Connector T12
345# IO-Bank 0
346# NET TP<8> LOC = D11 | IOSTANDARD=LVCMOS33; #
347# NET TP<9> LOC = C11 | IOSTANDARD=LVCMOS33; #
348
349# on Connector T14
350# IO-Bank 0
351# NET TP<10> LOC = D10 | IOSTANDARD=LVCMOS33; #
352# NET TP<11> LOC = C10 | IOSTANDARD=LVCMOS33; #
353# NET TP<12> LOC = A10 | IOSTANDARD=LVCMOS33; #
354# NET TP<13> LOC = B10 | IOSTANDARD=LVCMOS33; #
355
356# on Connector T16
357# IO-Bank 0
358# NET TP<14> LOC = A9 | IOSTANDARD=LVCMOS33; #
359# NET TP<15> LOC = B9 | IOSTANDARD=LVCMOS33; #
360# NET TP<16> LOC = A8 | IOSTANDARD=LVCMOS33; #
361# NET TP<17> LOC = B8 | IOSTANDARD=LVCMOS33; #
362
363# on Connector T8
364# IO-Bank 0
365# NET TP<18> LOC = C8 | IOSTANDARD=LVCMOS33; #
366# NET TP<19> LOC = D8 | IOSTANDARD=LVCMOS33; #
367# NET TP<20> LOC = C6 | IOSTANDARD=LVCMOS33; #
368# NET TP<21> LOC = B6 | IOSTANDARD=LVCMOS33; #
369
370# on Connector T9
371# IO-Bank 0
372# NET TP<22> LOC = C7 | IOSTANDARD=LVCMOS33; #
373# NET TP<23> LOC = B7 | IOSTANDARD=LVCMOS33; #
374
375# on Connector T11
376# IO-Bank 3
377# NET TP<24> LOC = Y1 | IOSTANDARD=LVCMOS33; #
378# NET TP<25> LOC = AA3 | IOSTANDARD=LVCMOS33; #
379# NET TP<26> LOC = AA2 | IOSTANDARD=LVCMOS33; #
380# NET TP<27> LOC = AC1 | IOSTANDARD=LVCMOS33; #
381
382# on Connector T13
383# IO-Bank 3
384# NET TP<28> LOC = AB1 | IOSTANDARD=LVCMOS33; #
385# NET TP<29> LOC = AC3 | IOSTANDARD=LVCMOS33; #
386# NET TP<30> LOC = AC2 | IOSTANDARD=LVCMOS33; #
387# NET TP<31> LOC = AD2 | IOSTANDARD=LVCMOS33; #
388
389# on Connector T15
390# NET TP<32> LOC = AD1 | IOSTANDARD=LVCMOS33; # IO-Bank 3
391# NET TP_in<33> LOC = AE2 | IOSTANDARD=LVCMOS33; # input only
392# NET TP_in<34> LOC = AE1 | IOSTANDARD=LVCMOS33; # input only
393
394
395# Board ID - inputs
396# local board-ID "solder programmable"
397# all on 'input only' pins
398#######################################################
399# NET brd_id<0> LOC = A13 | IOSTANDARD=LVCMOS33; #
400# NET brd_id<1> LOC = A17 | IOSTANDARD=LVCMOS33; #
401# NET brd_id<2> LOC = D12 | IOSTANDARD=LVCMOS33; #
402# NET brd_id<3> LOC = N25 | IOSTANDARD=LVCMOS33; #
403# NET brd_id<4> LOC = N26 | IOSTANDARD=LVCMOS33; #
404# NET brd_id<5> LOC = K24 | IOSTANDARD=LVCMOS33; #
405# NET brd_id<6> LOC = H24 | IOSTANDARD=LVCMOS33; #
406# NET brd_id<7> LOC = Y26 | IOSTANDARD=LVCMOS33; #
407
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