source: firmware/FTM/test_firmware/FTM_test3/FTM_definitions_test3.vhd@ 11111

Last change on this file since 11111 was 10046, checked in by vogler, 14 years ago
Test firmware for FTM hardware testing
File size: 1.2 KB
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1library IEEE;
2use IEEE.STD_LOGIC_1164.all;
3use IEEE.STD_LOGIC_ARITH.ALL;
4use IEEE.STD_LOGIC_UNSIGNED.ALL;
5-- use IEEE.NUMERIC_STD.ALL;
6
7package ftm_array_types is
8
9
10
11--- std_logic_vector (31 downto 0)
12--- type clk_cond_array_type is array (0 to 8) of integer range 0 to 2**32 - 1;
13
14 type clk_cond_array_type is array (0 to 8) of std_logic_vector (31 downto 0);
15 constant DEFAULT_Clk_Cond : clk_cond_array_type := (x"80000000", x"00038000", x"00010101", x"10000908", x"A0032A09", x"0082000B", x"020A000D", x"0830280E", x"1400FA0F");
16 -- This array contains the settings to be leaded in the clock conditioner
17 -- LMK03000 on the FTM board
18 -- The entrys of the array are:
19 -- R0 for Reset only, i.e. only bit 31 is set this resets the LMK0300
20 -- R0
21 -- R1
22 -- R8
23 -- R9
24 -- R11
25 -- R13
26 -- R14
27 -- R15
28 -- constant DEFAULT_Clk_Cond : clk_cond_array_type := (x"80000000", x"00010100", x"00010101", x"10000908", x"A0032A09", x"0082000B", x"020A000D", x"0830280E", x"2000960F");
29-- OLD: constant DEFAULT_Clk_Cond : clk_cond_array_type := (x"80000000", x"00038000", x"00010101", x"10000908", x"A0032A09", x"0082000B", x"020A000D", x"1830280E", x"1400FA0F");
30end ftm_array_types;
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