source: firmware/FTM/test_firmware/FTM_test3/FTM_test3.vhd@ 18558

Last change on this file since 18558 was 10046, checked in by vogler, 14 years ago
Test firmware for FTM hardware testing
  • Property svn:executable set to *
File size: 12.7 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 17 September 2010
6-- Design Name:
7-- Module Name: FTM_test3 - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Test firmware for FTM board: first test of the clock conditioner
12-- LMK03000
13--
14-- Dependencies:
15--
16-- Revision:
17-- Revision 0.01 - File Created
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21
22library IEEE;
23use IEEE.STD_LOGIC_1164.ALL;
24use IEEE.STD_LOGIC_ARITH.ALL;
25use IEEE.STD_LOGIC_UNSIGNED.ALL;
26
27---- Uncomment the following library declaration if instantiating
28---- any Xilinx primitives in this code.
29--library UNISIM;
30--use UNISIM.VComponents.all;
31
32
33library FTM_definitions_test3;
34USE FTM_definitions_test3.ftm_array_types.all;
35
36
37
38entity FTM_test3 is
39 port(
40
41
42-- Clock
43 clk : IN STD_LOGIC; -- external clock from
44 -- oscillator U47
45
46-- connection to the WIZnet W5300 ethernet controller
47-- on IO-Bank 1
48-------------------------------------------------------------------------------
49 -- W5300 data bus
50-- W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300
51
52
53 -- W5300 address bus
54-- W_A : out STD_LOGIC_VECTOR(9 downto 1); -- there is NO net W_A0 because
55 -- the W5300 is operated in the
56 -- 16-bit mode
57
58 -- W5300 controll signals
59 -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
60 -- W_CS is also routed to testpoint JP7
61-- W_CS : out STD_LOGIC; -- W5300 chip select
62-- W_INT : IN STD_LOGIC; -- interrupt
63-- W_RD : out STD_LOGIC; -- read
64-- W_WR : out STD_LOGIC; -- write
65-- W_RES : out STD_LOGIC; -- reset W5300 chip
66
67 -- W5300 buffer ready indicator
68-- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0);
69
70 -- testpoints (T18) associated with the W5300 on IO-bank 1
71-- W_T : inout STD_LOGIC_VECTOR(3 downto 0);
72
73
74
75-- SPI Interface
76-- connection to the EEPROM U36 (AL25L016M) and
77-- temperature sensors U45, U46, U48 and U49 (all MAX6662)
78-- on IO-Bank 1
79-------------------------------------------------------------------------------
80-- S_CLK : out STD_LOGIC; -- SPI clock
81
82 -- EEPROM
83-- MOSI : out STD_LOGIC; -- master out slave in
84-- MISO : in STD_LOGIC; -- master in slave out
85-- EE_CS : out STD_LOGIC; -- EEPROM chip select
86
87 -- temperature sensors U45, U46, U48 and U49
88-- SIO : inout STD_LOGIC; -- serial IO
89-- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select
90
91
92
93-- Trigger primitives inputs
94-- on IO-Bank 2
95-------------------------------------------------------------------------------
96-- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0
97-- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1
98-- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2
99-- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3
100
101
102
103-- NIM inputs
104------------------------------------------------------------------------------
105 -- on IO-Bank 3
106-- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input
107-- Veto : in STD_LOGIC; -- trigger veto input
108-- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs
109
110 -- on IO-Bank 0
111-- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available
112
113
114
115-- LEDs on IO-Banks 0 and 3
116-------------------------------------------------------------------------------
117-- LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red
118-- LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow
119 LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green
120
121
122
123-- Clock conditioner LMK03000
124-- on IO-Bank 3
125-------------------------------------------------------------------------------
126 CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock
127 LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable
128 DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data
129
130-- SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization
131 LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect
132
133
134
135
136-- various RS-485 Interfaces
137-- on IO-Bank 3
138-------------------------------------------------------------------------------
139 -- Bus 1: FTU slow control
140-- Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable
141-- Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable
142
143-- Bus1_RxD_0 : in STD_LOGIC; -- crate 0
144-- Bus1_TxD_0 : out STD_LOGIC;
145
146-- Bus1_RxD_1 : in STD_LOGIC; -- crate 1
147-- Bus1_TxD_1 : out STD_LOGIC;
148
149-- Bus1_RxD_2 : in STD_LOGIC; -- crate 2
150-- Bus1_TxD_2 : out STD_LOGIC;
151
152-- Bus1_RxD_3 : in STD_LOGIC; -- crate 3
153-- Bus1_TxD_3 : out STD_LOGIC;
154
155
156 -- Bus 2: Trigger-ID to FAD boards
157-- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable
158-- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable
159
160-- Bus2_RxD_0 : in STD_LOGIC; -- crate 0
161-- Bus2_TxD_0 : out STD_LOGIC;
162
163-- Bus2_RxD_1 : in STD_LOGIC; -- crate 1
164-- Bus2_TxD_1 : out STD_LOGIC;
165
166-- Bus2_RxD_2 : in STD_LOGIC; -- crate 2
167-- Bus2_TxD_2 : out STD_LOGIC;
168
169-- Bus2_RxD_3 : in STD_LOGIC; -- crate 3
170-- Bus2_TxD_3 : out STD_LOGIC;
171
172
173-- auxiliary access
174-- Aux_Rx_D : in STD_LOGIC; --
175-- Aux_Tx_D : out STD_LOGIC; --
176-- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable
177-- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID
178
179
180-- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
181-- TrID_Rx_D : in STD_LOGIC; --
182-- TrID_Tx_D : out STD_LOGIC; --
183
184
185-- Crate-Resets
186-- on IO-Bank 3
187-------------------------------------------------------------------------------
188-- Crate_Res0 : out STD_LOGIC; --
189-- Crate_Res1 : out STD_LOGIC; --
190-- Crate_Res2 : out STD_LOGIC; --
191-- Crate_Res3 : out STD_LOGIC; --
192
193
194-- Busy signals from the FAD boards
195-- on IO-Bank 3
196-------------------------------------------------------------------------------
197-- Busy0 : in STD_LOGIC; --
198-- Busy1 : in STD_LOGIC; --
199-- Busy2 : in STD_LOGIC; --
200-- Busy3 : in STD_LOGIC; --
201
202
203
204-- NIM outputs
205-- on IO-Bank 0
206-- LVDS output at the FPGA followed by LVDS to NIM conversion stage
207-------------------------------------------------------------------------------
208-- calibration
209-- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+
210-- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1-
211-- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+
212-- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2-
213
214-- auxiliarry / spare NIM outputs
215-- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+
216-- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0-
217-- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+
218-- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1-
219
220
221
222-- fast control signal outputs
223-- LVDS output at the FPGA followed by LVDS to NIM conversion stage
224-- conversion stage
225-------------------------------------------------------------------------------
226-- RES_p : out STD_LOGIC; -- RES+ Reset
227-- RES_n : out STD_LOGIC; -- RES- IO-Bank 0
228
229-- TRG_p : out STD_LOGIC; -- TRG+ Trigger
230-- TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0
231
232-- TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker
233-- TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2
234 TIM_Sel : out STD_LOGIC -- Time Marker selector on
235 -- IO-Bank 2
236
237-- CLD_FPGA : out STD_LOGIC; -- DRS-Clock feedback into FPGA
238
239
240
241-- LVDS calibration outputs
242-- on IO-Bank 0
243-------------------------------------------------------------------------------
244-- to connector J13
245-- Cal_0_p : out STD_LOGIC;
246-- Cal_0_n : out STD_LOGIC;
247-- Cal_1_p : out STD_LOGIC;
248-- Cal_1_n : out STD_LOGIC;
249-- Cal_2_p : out STD_LOGIC;
250-- Cal_2_n : out STD_LOGIC;
251-- Cal_3_p : out STD_LOGIC;
252-- Cal_3_n : out STD_LOGIC;
253
254-- to connector J12
255-- Cal_4_p : out STD_LOGIC;
256-- Cal_4_n : out STD_LOGIC;
257-- Cal_5_p : out STD_LOGIC;
258-- Cal_5_n : out STD_LOGIC;
259-- Cal_6_p : out STD_LOGIC;
260-- Cal_6_n : out STD_LOGIC;
261-- Cal_7_p : out STD_LOGIC;
262-- Cal_7_n : out STD_LOGIC;
263
264
265-- Testpoints
266-------------------------------------------------------------------------------
267-- TP : inout STD_LOGIC_VECTOR(32 downto 0)
268-- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only
269
270-- Board ID - inputs
271-- local board-ID "solder programmable"
272-- all on 'input only' pins
273-------------------------------------------------------------------------------
274-- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only
275 );
276end FTM_test3;
277
278
279architecture Behavioral of FTM_test3 is
280
281 component FTM_test1_dcm
282 port ( CLKIN_IN : in std_logic;
283 CLKFX_OUT : out std_logic;
284 CLKIN_IBUFG_OUT : out std_logic);
285 end component;
286
287
288component FTM_test3_microwire_interface IS
289 PORT(
290 clk : IN std_logic;
291 clk_uwire : OUT std_logic; --- IN or OUT ?
292 data_uwire : OUT std_logic;
293 le_uwire : OUT std_logic;
294 clk_cond_array : IN clk_cond_array_type;
295 config_start : IN std_logic;
296 config_ready : OUT std_logic;
297 config_started : OUT std_logic
298 );
299end component;
300
301
302
303
304 signal clk_250M_sig : STD_LOGIC;
305-- signal enable_sig : STD_LOGIC;
306 signal reset_sig : STD_LOGIC := '0'; -- initialize reset to 0 at power up
307
308 type FTM_test3_StateType is (Running);
309 signal FTM_test3_State, FTM_test3_NextState: FTM_test3_StateType;
310
311 signal config_ready_sig : STD_LOGIC;
312 signal clk_uwire_sig : STD_LOGIC;
313
314 signal clk_cond_array_sig : clk_cond_array_type;
315
316 signal config_puls_cnt : integer range 0 to 2000 := 0;
317
318
319
320begin
321
322 Inst_FTM_test1_dcm : FTM_test1_dcm
323 port map(
324 CLKIN_IN => clk,
325 CLKFX_OUT => clk_250M_sig,
326 CLKIN_IBUFG_OUT => open
327 );
328
329
330
331 Inst_FTM_test3_microwire_interface:FTM_test3_microwire_interface
332 port map (
333 clk => clk_250M_sig,
334 clk_uwire => clk_uwire_sig,
335 data_uwire => DATA_Clk_Cond,
336 le_uwire => LE_Clk_Cond,
337 clk_cond_array => clk_cond_array_sig, -- default array 2GHz DRS and 250MHz TIM
338
339 config_start => reset_sig,
340 config_ready => config_ready_sig,
341 config_started => open
342 );
343
344
345 LED_gn(0) <= NOT (config_ready_sig AND LD_Clk_Cond); -- indicate that PLL is locked
346 TIM_Sel <= '1'; -- timing calibration signal from Clock
347 -- conditioner on TIM line
348
349 LED_gn(1) <= '1'; -- switch off unused green LED
350
351 CLK_Clk_Cond <= clk_uwire_sig;
352 clk_cond_array_sig <= DEFAULT_Clk_Cond; -- Default Clock conditioner settings
353 -- 2 GHz DRS and 250 MHz TIM
354
355
356
357
358
359
360
361--FTM main state machine
362 FTM_test3_Registers: process (clk_250M_sig)
363 begin
364 if Rising_edge(clk_250M_sig) then
365 if (config_puls_cnt < 2000) then
366 config_puls_cnt <= config_puls_cnt + 1;
367 end if;
368
369 if (config_puls_cnt < 1000) then
370 reset_sig <= '0';
371 elsif ((config_puls_cnt > 999) and (config_puls_cnt < 1900)) then
372 reset_sig <= '1';
373 else
374 reset_sig <= '0';
375 end if;
376
377 end if;
378 end process FTM_test3_Registers;
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394 --FTU main state machine (two-process implementation)
395
396-- FTM_test3_Registers: process (clk_250M_sig) -- TBR
397-- begin
398-- if Rising_edge(clk_250M_sig) then
399-- FTM_test3_State <= FTM_test3_NextState;
400-- end if;
401-- end process FTM_test3_Registers;
402
403-- FTM_test3_C_logic: process (FTM_test3_State)
404-- begin
405-- FTM_test3_NextState <= FTM_test3_State;
406-- case FTM_test3_State is
407-- when Running =>
408-- reset_sig <= '0';
409-- end case;
410-- end process FTM_test3_C_logic;
411
412
413
414
415
416
417
418
419
420end Behavioral;
421
422
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