source: firmware/FTM/test_firmware/FTM_test3/FTM_test3_microwire_interface.vhd@ 10094

Last change on this file since 10094 was 10046, checked in by vogler, 14 years ago
Test firmware for FTM hardware testing
File size: 3.6 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 07/14/2010
6-- Design Name:
7-- Module Name: FTM_test3_microwire_interface - Behavioral
8-- (based on FTU_test5_spi_interface - Behavioral)
9-- Project Name:
10-- Target Devices:
11-- Tool versions:
12-- Description: Based on VHDL Entity FACT_FAD_lib.spi_interface.symbol
13--
14-- Dependencies:
15--
16-- Revision:
17-- Revision 0.01 - File Created
18-- Additional Comments:
19--
20--
21-- modified by Patrick Vogler, September 17 2010
22-- for use as a microwire interface to the clock conditioner LMK03000
23-- on the FTM board
24----------------------------------------------------------------------------------
25library IEEE;
26use IEEE.STD_LOGIC_1164.ALL;
27use IEEE.STD_LOGIC_ARITH.ALL;
28use IEEE.STD_LOGIC_UNSIGNED.ALL;
29
30library FTM_definitions_test3;
31USE FTM_definitions_test3.ftm_array_types.all;
32
33-------------------------------------------------------------------------------
34---- Uncomment the following library declaration if instantiating
35---- any Xilinx primitives in this code.
36--library UNISIM;
37--use UNISIM.VComponents.all;
38
39ENTITY FTM_test3_microwire_interface IS
40 PORT(
41 clk : IN std_logic; -- 250MHz
42 clk_uwire : OUT std_logic; -- sclk
43 data_uwire : OUT std_logic := '0'; -- mosi
44 le_uwire : OUT std_logic := '1'; -- Latch Enable = chip select
45 clk_cond_array : IN clk_cond_array_type; -- data to be loaded
46 -- into the clock conditioner
47 config_start : IN std_logic;
48 config_ready : OUT std_logic := '0';
49 config_started : OUT std_logic := '0'
50 );
51END FTM_test3_microwire_interface;
52
53
54ARCHITECTURE struct OF FTM_test3_microwire_interface IS
55
56 -- Internal signal declarations
57 SIGNAL clk_uwire_sig : std_logic;
58
59
60 -- Component Declarations
61 COMPONENT FTM_test3_microwire_clock_gen
62 GENERIC (
63 CLK_DIVIDER : integer := 125 --2 MHz @ 250 MHz
64 );
65 PORT (
66 clk : IN std_logic;
67 sclk : OUT std_logic := '0'
68 );
69 END COMPONENT;
70
71
72 COMPONENT FTM_test3_microwire_controller
73 PORT (
74 clk_uwire : IN std_logic; -- sclk
75 data_uwire : OUT std_logic := '0'; -- mosi
76 le_uwire : OUT std_logic := '1'; -- Latch Enable = chip select
77 clk_cond_array : IN clk_cond_array_type; -- data to be loaded
78 -- into the clock conditioner
79 config_start : IN std_logic;
80 config_ready : OUT std_logic := '0';
81 config_started : OUT std_logic := '0'
82 );
83 END COMPONENT;
84
85
86
87BEGIN
88
89 -- Instance port mappings.
90 Inst_FTM_test3_microwire_clock_gen : FTM_test3_microwire_clock_gen
91 GENERIC MAP (
92 CLK_DIVIDER => 125 --2 MHz @ 250 MHz
93 )
94 PORT MAP (
95 clk => clk,
96 sclk => clk_uwire_sig
97 );
98
99 Inst_FTM_test3_microwire_controller : FTM_test3_microwire_controller
100 PORT MAP (
101 clk_uwire => clk_uwire_sig,
102 data_uwire => data_uwire,
103 le_uwire => le_uwire,
104 clk_cond_array => clk_cond_array,
105 config_start => config_start,
106 config_ready => config_ready,
107 config_started => config_started
108 );
109
110 clk_uwire<= clk_uwire_sig;
111
112END struct;
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