| 1 | ########################################################
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| 2 | # FTM Board
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| 3 | # FACT Trigger Master
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| 4 | #
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| 5 | # Pin location constraints
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| 6 | #
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| 7 | # by Patrick Vogler
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| 8 | # 4 October 2010
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| 9 | #
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| 10 | # Pin location for FTM test 4 (ethernet controller)
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| 11 | ########################################################
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| 12 |
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| 13 |
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| 14 | #Clock
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| 15 | #######################################################
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| 16 | NET clk LOC = Y14 | IOSTANDARD=LVCMOS33; # FPGA-CLK from oscillator U47
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| 17 |
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| 18 |
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| 19 | # Ethernet Interface
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| 20 | # connection to the WIZnet W5300 ethernet controller (U37)
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| 21 | # on IO-Bank 1
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| 22 | #######################################################
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| 23 | # data bus
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| 24 | NET W_D<0> LOC = M22 | IOSTANDARD=LVCMOS33; # 16-bit data bus to W5300
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| 25 | NET W_D<1> LOC = L22 | IOSTANDARD=LVCMOS33; #
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| 26 | NET W_D<2> LOC = K23 | IOSTANDARD=LVCMOS33; #
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| 27 | NET W_D<3> LOC = K25 | IOSTANDARD=LVCMOS33; #
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| 28 | NET W_D<4> LOC = K26 | IOSTANDARD=LVCMOS33; #
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| 29 | NET W_D<5> LOC = J22 | IOSTANDARD=LVCMOS33; #
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| 30 | NET W_D<6> LOC = J23 | IOSTANDARD=LVCMOS33; #
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| 31 | NET W_D<7> LOC = G23 | IOSTANDARD=LVCMOS33; #
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| 32 | NET W_D<8> LOC = G24 | IOSTANDARD=LVCMOS33; #
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| 33 | NET W_D<9> LOC = F24 | IOSTANDARD=LVCMOS33; #
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| 34 | NET W_D<10> LOC = F25 | IOSTANDARD=LVCMOS33; #
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| 35 | NET W_D<11> LOC = E24 | IOSTANDARD=LVCMOS33; #
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| 36 | NET W_D<12> LOC = E26 | IOSTANDARD=LVCMOS33; #
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| 37 | NET W_D<13> LOC = D24 | IOSTANDARD=LVCMOS33; #
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| 38 | NET W_D<14> LOC = D26 | IOSTANDARD=LVCMOS33; #
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| 39 | NET W_D<15> LOC = D25 | IOSTANDARD=LVCMOS33; #
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| 40 |
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| 41 | # W5300 address bus
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| 42 | NET W_A<1> LOC = AA25 | IOSTANDARD=LVCMOS33; # there is NO net W_A0 because
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| 43 | NET W_A<2> LOC = AA24 | IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode
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| 44 | NET W_A<3> LOC = AA23 | IOSTANDARD=LVCMOS33; # see W5300 datasheet
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| 45 | NET W_A<4> LOC = Y25 | IOSTANDARD=LVCMOS33; #
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| 46 | NET W_A<5> LOC = Y24 | IOSTANDARD=LVCMOS33; #
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| 47 | NET W_A<6> LOC = Y23 | IOSTANDARD=LVCMOS33; #
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| 48 | NET W_A<7> LOC = W23 | IOSTANDARD=LVCMOS33; #
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| 49 | NET W_A<8> LOC = V25 | IOSTANDARD=LVCMOS33; #
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| 50 | NET W_A<9> LOC = V24 | IOSTANDARD=LVCMOS33; #
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| 51 |
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| 52 | # W5300 controll signals
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| 53 | # the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
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| 54 | # W_CS is also routed to testpoint JP7
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| 55 | NET W_CS LOC = T20 | IOSTANDARD=LVCMOS33; # W5300 chip select
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| 56 | NET W_INT LOC = U22 | IOSTANDARD=LVCMOS33; # interrupt
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| 57 | NET W_RD LOC = R20 | IOSTANDARD=LVCMOS33; # read
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| 58 | NET W_WR LOC = P22 | IOSTANDARD=LVCMOS33; # write
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| 59 | NET W_RES LOC = U23 | IOSTANDARD=LVCMOS33; # reset W5300 chip
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| 60 |
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| 61 | # W5300 buffer ready indicator
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| 62 | # NET W_BRDY<0> LOC = AB26 | IOSTANDARD=LVCMOS33; #
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| 63 | # NET W_BRDY<1> LOC = AC26 | IOSTANDARD=LVCMOS33; #
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| 64 | # NET W_BRDY<2> LOC = AC25 | IOSTANDARD=LVCMOS33; #
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| 65 | # NET W_BRDY<3> LOC = AD26 | IOSTANDARD=LVCMOS33; #
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| 66 |
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| 67 | # W5300 associated testpoints
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| 68 | # NET W_T<0> LOC = N21 | IOSTANDARD=LVCMOS33; #
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| 69 | # NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; #
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| 70 | # NET W_T<2> LOC = K21 | IOSTANDARD=LVCMOS33; #
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| 71 | # NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; #
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| 72 |
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| 73 |
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| 74 | # SPI Interface
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| 75 | # connection to the EEPROM U36 (AL25L016M) and the temperature
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| 76 | # sensors U45, U46, U48 and U49 (all MAX6662)
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| 77 | # on IO-Bank 1
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| 78 | #######################################################
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| 79 | # NET S_CLK LOC = U20 | IOSTANDARD=LVCMOS33; # SPI clock
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| 80 |
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| 81 | # EEPROM
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| 82 | # NET MOSI LOC = AA22 | IOSTANDARD=LVCMOS33; # master out slave in
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| 83 | # NET MISO LOC = V22 | IOSTANDARD=LVCMOS33; # master in slave out
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| 84 | # NET EE_CS LOC = G22 | IOSTANDARD=LVCMOS33; # master out slave in
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| 85 |
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| 86 | # temperature sensors
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| 87 | # NET SIO LOC = F22 | IOSTANDARD=LVCMOS33; # serial IO
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| 88 | # NET TS_CS<0> LOC = H21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select0
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| 89 | # NET TS_CS<1> LOC = J21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select1
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| 90 | # NET TS_CS<2> LOC = C25 | IOSTANDARD=LVCMOS33; # temperature sensors chip select2
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| 91 | # NET TS_CS<3> LOC = C26 | IOSTANDARD=LVCMOS33; # temperature sensors chip select3
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| 92 |
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| 93 |
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| 94 | # Trigger primitives inputs
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| 95 | # on IO-Bank 2
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| 96 | #######################################################
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| 97 | # crate 0
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| 98 | # crate A
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| 99 | # NET Trig_Prim_A<0> LOC = AC6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0>
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| 100 | # NET Trig_Prim_A<1> LOC = AD6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1>
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| 101 | # NET Trig_Prim_A<2> LOC = AF3 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2>
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| 102 | # NET Trig_Prim_A<3> LOC = AE4 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3>
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| 103 | # NET Trig_Prim_A<4> LOC = AE6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4>
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| 104 | # NET Trig_Prim_A<5> LOC = AE7 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5>
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| 105 | # NET Trig_Prim_A<6> LOC = AE8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6>
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| 106 | # NET Trig_Prim_A<7> LOC = AC8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7>
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| 107 | # NET Trig_Prim_A<8> LOC = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8>
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| 108 | # NET Trig_Prim_A<9> LOC = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9>
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| 109 |
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| 110 | # crate 1
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| 111 | # crate B
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| 112 | # NET Trig_Prim_B<0> LOC = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0>
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| 113 | # NET Trig_Prim_B<1> LOC = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1>
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| 114 | # NET Trig_Prim_B<2> LOC = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2>
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| 115 | # NET Trig_Prim_B<3> LOC = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3>
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| 116 | # NET Trig_Prim_B<4> LOC = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4>
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| 117 | # NET Trig_Prim_B<5> LOC = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5>
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| 118 | # NET Trig_Prim_B<6> LOC = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6>
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| 119 | # NET Trig_Prim_B<7> LOC = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7>
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| 120 | # NET Trig_Prim_B<8> LOC = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8>
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| 121 | # NET Trig_Prim_B<9> LOC = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9>
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| 122 |
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| 123 | # crate 2
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| 124 | # crate C
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| 125 | # NET Trig_Prim_C<0> LOC = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0>
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| 126 | # NET Trig_Prim_C<1> LOC = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1>
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| 127 | # NET Trig_Prim_C<2> LOC = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2>
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| 128 | # NET Trig_Prim_C<3> LOC = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3>
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| 129 | # NET Trig_Prim_C<4> LOC = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4>
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| 130 | # NET Trig_Prim_C<5> LOC = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5>
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| 131 | # NET Trig_Prim_C<6> LOC = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6>
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| 132 | # NET Trig_Prim_C<7> LOC = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7>
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| 133 | # NET Trig_Prim_C<8> LOC = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8>
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| 134 | # NET Trig_Prim_C<9> LOC = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9>
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| 135 |
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| 136 | # crate 3
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| 137 | # crate D
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| 138 | # NET Trig_Prim_D<0> LOC = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0>
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| 139 | # NET Trig_Prim_D<1> LOC = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1>
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| 140 | # NET Trig_Prim_D<2> LOC = AC9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2>
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| 141 | # NET Trig_Prim_D<3> LOC = AB9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3>
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| 142 | # NET Trig_Prim_D<4> LOC = AB7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4>
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| 143 | # NET Trig_Prim_D<5> LOC = AF8 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5>
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| 144 | # NET Trig_Prim_D<6> LOC = AF4 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6>
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| 145 | # NET Trig_Prim_D<7> LOC = AF5 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7>
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| 146 | # NET Trig_Prim_D<8> LOC = AD7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8>
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| 147 | # NET Trig_Prim_D<9> LOC = AE3 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9>
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| 148 |
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| 149 |
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| 150 | # NIM inputs
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| 151 | #######################################################
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| 152 | # on IO-Bank 3
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| 153 | # NET ext_Trig<1> LOC = B1 | IOSTANDARD=LVCMOS33; #
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| 154 | # NET ext_Trig<2> LOC = B2 | IOSTANDARD=LVCMOS33; #
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| 155 | # NET Veto LOC = E4 | IOSTANDARD=LVCMOS33; #
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| 156 | # NET NIM_In<0> LOC = D3 | IOSTANDARD=LVCMOS33; #
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| 157 | # NET NIM_In<1> LOC = F4 | IOSTANDARD=LVCMOS33; #
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| 158 | # NET NIM_In<2> LOC = E3 | IOSTANDARD=LVCMOS33; #
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| 159 |
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| 160 | # on IO-Bank 0
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| 161 | # NET NIM_In3_GCLK LOC = K14 | IOSTANDARD=LVCMOS33; # input with global clock buffer
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| 162 | # available
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| 163 |
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| 164 |
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| 165 | # LEDs
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| 166 | # on IO-Banks 0 and 3
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| 167 | #######################################################
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| 168 | # red
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| 169 | # NET LED_red<0> LOC = D6 | IOSTANDARD=LVCMOS33; # IO-Bank 0
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| 170 | # NET LED_red<1> LOC = A4 | IOSTANDARD=LVCMOS33; # IO-Bank 0
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| 171 | # NET LED_red<2> LOC = E1 | IOSTANDARD=LVCMOS33; # IO-Bank 3
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| 172 | # NET LED_red<3> LOC = J5 | IOSTANDARD=LVCMOS33; # IO-Bank 3
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| 173 |
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| 174 | # yellow
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| 175 | # NET LED_ye<0> LOC = C5 | IOSTANDARD=LVCMOS33; # IO-Bank 0
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| 176 | # NET LED_ye<1> LOC = B3 | IOSTANDARD=LVCMOS33; # IO-Bank 0
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| 177 |
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| 178 | # green
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| 179 | # NET LED_gn<0> LOC = B4 | IOSTANDARD=LVCMOS33; # IO-Bank 0
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| 180 | # NET LED_gn<1> LOC = A3 | IOSTANDARD=LVCMOS33; # IO-Bank 0
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| 181 |
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| 182 |
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| 183 | # Clock conditioner LMK03000
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| 184 | # on IO-Bank 3
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| 185 | #######################################################
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| 186 | # NET CLK_Clk_Cond LOC = G4 | IOSTANDARD=LVCMOS33; # IO-Bank 3
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| 187 | # NET LE_Clk_Cond LOC = F2 | IOSTANDARD=LVCMOS33; # IO-Bank 3
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| 188 | # NET LD_Clk_Cond LOC = J4 | IOSTANDARD=LVCMOS33; # IO-Bank 3
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| 189 | # NET DATA_Clk_Cond LOC = F3 | IOSTANDARD=LVCMOS33; # IO-Bank 3
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| 190 | # NET SYNC_Clk_Cond LOC = H2 | IOSTANDARD=LVCMOS33; # IO-Bank 3
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| 191 |
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| 192 |
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| 193 | # various RS-485 Interfaces
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| 194 | # on IO-Bank 3
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| 195 | #######################################################
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| 196 | # Bus 1: FTU slow control
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| 197 | # NET Bus1_Tx_En LOC = H1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 198 | # NET Bus1_Rx_En LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 199 |
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| 200 | # crate 0
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| 201 | # NET Bus1_RxD_0 LOC = K3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 202 | # NET Bus1_TxD_0 LOC = L3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 203 |
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| 204 | # crate 1
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| 205 | # NET Bus1_RxD_1 LOC = M2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 206 | # NET Bus1_TxD_1 LOC = N4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 207 |
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| 208 | # crate 2
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| 209 | # NET Bus1_RxD_2 LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 210 | # NET Bus1_TxD_2 LOC = P4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 211 |
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| 212 | # crate 3
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| 213 | # NET Bus1_RxD_3 LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 214 | # NET Bus1_TxD_3 LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 215 |
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| 216 |
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| 217 | # Bus 2: Trigger-ID to FAD boards
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| 218 | # NET Bus2_Tx_En LOC = K2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 219 | # NET Bus2_Rx_En LOC = K4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 220 |
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| 221 | # crate 0
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| 222 | # NET Bus2_RxD_0 LOC = L4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 223 | # NET Bus2_TxD_0 LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 224 |
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| 225 | # crate 1
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| 226 | # NET Bus2_RxD_1 LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 227 | # NET Bus2_TxD_1 LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 228 |
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| 229 | # crate 2
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| 230 | # NET Bus2_RxD_2 LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 231 | # NET Bus2_TxD_2 LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 232 |
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| 233 | # crate 3
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| 234 | # NET Bus2_RxD_3 LOC = U4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 235 | # NET Bus2_TxD_3 LOC = U2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 236 |
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| 237 |
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| 238 | # auxiliary access
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| 239 | # NET Aux_Rx_D LOC = W3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 240 | # NET Aux_Tx_D LOC = Y2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 241 | # NET Aux_Rx_En LOC = W4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable
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| 242 | # NET Aux_Tx_En LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary
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| 243 | # Trigger-ID
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| 244 |
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| 245 | # auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
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| 246 | # NET TrID_Rx_D LOC = U6 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 247 | # NET TrID_Tx_D LOC = T7 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 248 |
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| 249 |
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| 250 | # Crate-Resets
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| 251 | # on IO-Bank 3
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| 252 | #######################################################
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| 253 | # NET Crate_Res0 LOC = M1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 254 | # NET Crate_Res1 LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 255 | # NET Crate_Res2 LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 256 | # NET Crate_Res3 LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 257 |
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| 258 |
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| 259 | # Busy signals from the FAD boards
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| 260 | # on IO-Bank 3
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| 261 | #######################################################
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| 262 | # NET Busy0 LOC = M4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 263 | # NET Busy1 LOC = P2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 264 | # NET Busy2 LOC = R4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 265 | # NET Busy3 LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
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| 266 |
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| 267 |
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| 268 | # NIM outputs
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| 269 | # on IO-Bank 0
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| 270 | # LVDS output at the FPGA followed by LVDS to NIM
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| 271 | # conversion stage
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| 272 | #######################################################
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| 273 | # calibration
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| 274 | # NET Cal_NIM1_p LOC = D18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM1+
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| 275 | # NET Cal_NIM1_n LOC = C18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM1-
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| 276 | # NET Cal_NIM2_p LOC = B18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM2+
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| 277 | # NET Cal_NIM2_n LOC = A18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM2-
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| 278 |
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| 279 | # auxiliarry / spare NIM outputs
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| 280 | # NET NIM_Out0_p LOC = C17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out0+
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| 281 | # NET NIM_Out0_n LOC = B17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out0-
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| 282 | # NET NIM_Out1_p LOC = D17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # NIM_Out1+
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| 283 | # NET NIM_Out1_n LOC = C16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out1-
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| 284 |
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| 285 |
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| 286 | # fast control signal outputs
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| 287 | # LVDS output at the FPGA followed by LVDS to NIM
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| 288 | # conversion stage
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| 289 | #######################################################
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| 290 | # NET RES_p LOC = D16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES+ Reset
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| 291 | # NET RES_n LOC = C15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES- IO-Bank 0
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| 292 |
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| 293 | # NET TRG_p LOC = B15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG+ Trigger
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| 294 | # NET TRG_n LOC = A15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG- IO-Bank 0
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| 295 |
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| 296 | # NET TIM_Run_p LOC = AF25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run+ Time Marker
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| 297 | # NET TIM_Run_n LOC = AE25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run-
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| 298 | # on IO-Bank2
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| 299 | # NET TIM_Sel LOC = AD22 | IOSTANDARD=LVCMOS33; # Time Marker selector
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| 300 | # IO-Bank 2
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| 301 | # NET CLD_FPGA LOC = AA14 | IOSTANDARD=LVCMOS33; # DRS-Clock feedback into FPGA
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| 302 |
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| 303 |
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| 304 | # LVDS calibration outputs
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| 305 | # on IO-Bank 0
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| 306 | #######################################################
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| 307 | # to connector J13
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| 308 | # NET Cal_0_p LOC = D22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0+
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| 309 | # NET Cal_0_n LOC = C22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0-
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| 310 | # NET Cal_1_p LOC = D23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1+
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| 311 | # NET Cal_1_n LOC = C23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1-
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| 312 | # NET Cal_2_p LOC = B23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2+
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| 313 | # NET Cal_2_n LOC = A22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2-
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| 314 | # NET Cal_3_p LOC = C21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3+
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| 315 | # NET Cal_3_n LOC = B21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3-
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| 316 |
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| 317 | # to connector J12
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| 318 | # NET Cal_4_p LOC = E21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4+
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| 319 | # NET Cal_4_n LOC = D21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4-
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| 320 | # NET Cal_5_p LOC = D20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5+
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| 321 | # NET Cal_5_n LOC = C20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5-
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| 322 | # NET Cal_6_p LOC = B20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6+
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| 323 | # NET Cal_6_n LOC = A20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6-
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| 324 | # NET Cal_7_p LOC = B19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7+
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| 325 | # NET Cal_7_n LOC = A19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7-
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| 326 |
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| 327 |
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| 328 | # Testpoints
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| 329 | ######################################################
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| 330 | # Connector T7
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| 331 | # IO-Bank 0
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| 332 | # NET TP<0> LOC = B14 | IOSTANDARD=LVCMOS33; #
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| 333 | # NET TP<1> LOC = A14 | IOSTANDARD=LVCMOS33; #
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| 334 | # NET TP<2> LOC = C13 | IOSTANDARD=LVCMOS33; #
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| 335 | # NET TP<3> LOC = B13 | IOSTANDARD=LVCMOS33; #
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| 336 |
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| 337 | # Connector T10
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| 338 | # IO-Bank 0
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| 339 | # NET TP<4> LOC = D13 | IOSTANDARD=LVCMOS33; #
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| 340 | # NET TP<5> LOC = C12 | IOSTANDARD=LVCMOS33; #
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| 341 | # NET TP<6> LOC = B12 | IOSTANDARD=LVCMOS33; #
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| 342 | # NET TP<7> LOC = A12 | IOSTANDARD=LVCMOS33; #
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| 343 |
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| 344 | # on Connector T12
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| 345 | # IO-Bank 0
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| 346 | # NET TP<8> LOC = D11 | IOSTANDARD=LVCMOS33; #
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| 347 | # NET TP<9> LOC = C11 | IOSTANDARD=LVCMOS33; #
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| 348 |
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| 349 | # on Connector T14
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| 350 | # IO-Bank 0
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| 351 | # NET TP<10> LOC = D10 | IOSTANDARD=LVCMOS33; #
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| 352 | # NET TP<11> LOC = C10 | IOSTANDARD=LVCMOS33; #
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| 353 | # NET TP<12> LOC = A10 | IOSTANDARD=LVCMOS33; #
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| 354 | # NET TP<13> LOC = B10 | IOSTANDARD=LVCMOS33; #
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| 355 |
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| 356 | # on Connector T16
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| 357 | # IO-Bank 0
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| 358 | # NET TP<14> LOC = A9 | IOSTANDARD=LVCMOS33; #
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| 359 | # NET TP<15> LOC = B9 | IOSTANDARD=LVCMOS33; #
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| 360 | # NET TP<16> LOC = A8 | IOSTANDARD=LVCMOS33; #
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| 361 | # NET TP<17> LOC = B8 | IOSTANDARD=LVCMOS33; #
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| 362 |
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| 363 | # on Connector T8
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| 364 | # IO-Bank 0
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| 365 | # NET TP<18> LOC = C8 | IOSTANDARD=LVCMOS33; #
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| 366 | # NET TP<19> LOC = D8 | IOSTANDARD=LVCMOS33; #
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| 367 | # NET TP<20> LOC = C6 | IOSTANDARD=LVCMOS33; #
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| 368 | # NET TP<21> LOC = B6 | IOSTANDARD=LVCMOS33; #
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| 369 |
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| 370 | # on Connector T9
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| 371 | # IO-Bank 0
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| 372 | # NET TP<22> LOC = C7 | IOSTANDARD=LVCMOS33; #
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| 373 | # NET TP<23> LOC = B7 | IOSTANDARD=LVCMOS33; #
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| 374 |
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| 375 | # on Connector T11
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| 376 | # IO-Bank 3
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| 377 | # NET TP<24> LOC = Y1 | IOSTANDARD=LVCMOS33; #
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| 378 | # NET TP<25> LOC = AA3 | IOSTANDARD=LVCMOS33; #
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| 379 | # NET TP<26> LOC = AA2 | IOSTANDARD=LVCMOS33; #
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| 380 | # NET TP<27> LOC = AC1 | IOSTANDARD=LVCMOS33; #
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| 381 |
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| 382 | # on Connector T13
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| 383 | # IO-Bank 3
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| 384 | # NET TP<28> LOC = AB1 | IOSTANDARD=LVCMOS33; #
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| 385 | # NET TP<29> LOC = AC3 | IOSTANDARD=LVCMOS33; #
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| 386 | # NET TP<30> LOC = AC2 | IOSTANDARD=LVCMOS33; #
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| 387 | # NET TP<31> LOC = AD2 | IOSTANDARD=LVCMOS33; #
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| 388 |
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| 389 | # on Connector T15
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| 390 | # NET TP<32> LOC = AD1 | IOSTANDARD=LVCMOS33; # IO-Bank 3
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| 391 | # NET TP_in<33> LOC = AE2 | IOSTANDARD=LVCMOS33; # input only
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| 392 | # NET TP_in<34> LOC = AE1 | IOSTANDARD=LVCMOS33; # input only
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| 393 |
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| 394 |
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| 395 | # Board ID - inputs
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| 396 | # local board-ID "solder programmable"
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| 397 | # all on 'input only' pins
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| 398 | #######################################################
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| 399 | # NET brd_id<0> LOC = A13 | IOSTANDARD=LVCMOS33; #
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| 400 | # NET brd_id<1> LOC = A17 | IOSTANDARD=LVCMOS33; #
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| 401 | # NET brd_id<2> LOC = D12 | IOSTANDARD=LVCMOS33; #
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| 402 | # NET brd_id<3> LOC = N25 | IOSTANDARD=LVCMOS33; #
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| 403 | # NET brd_id<4> LOC = N26 | IOSTANDARD=LVCMOS33; #
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| 404 | # NET brd_id<5> LOC = K24 | IOSTANDARD=LVCMOS33; #
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| 405 | # NET brd_id<6> LOC = H24 | IOSTANDARD=LVCMOS33; #
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| 406 | # NET brd_id<7> LOC = Y26 | IOSTANDARD=LVCMOS33; #
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| 407 |
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