| 1 | -- Package File Template
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| 2 | --
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| 3 | -- Purpose: This package defines supplemental types, subtypes,
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| 4 | -- constants, and functions
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| 5 |
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| 6 |
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| 7 | library IEEE;
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| 8 | use IEEE.STD_LOGIC_1164.all;
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| 9 | use IEEE.STD_LOGIC_ARITH.ALL;
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| 10 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
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| 11 | -- use IEEE.NUMERIC_STD.ALL;
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| 12 |
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| 13 | package ftm_definitions is
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| 14 |
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| 15 |
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| 16 | -- Declare constants
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| 17 |
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| 18 | -- Network Settings
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| 19 | type mac_type is array (0 to 2) of std_logic_vector (15 downto 0);
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| 20 | constant MAC_ADDRESS : mac_type := (X"0011", X"9561", X"97B4");
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| 21 |
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| 22 | type ip_type is array (0 to 3) of integer;
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| 23 | constant NETMASK : ip_type := (255, 255, 248, 0);
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| 24 | constant IP_ADDRESS : ip_type := (192, 33, 99, 226);
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| 25 | constant GATEWAY : ip_type := (192, 33, 96, 1);
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| 26 | constant FIRST_PORT : integer := 5000;
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| 27 |
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| 28 | constant PACKAGE_VERSION : std_logic_vector(7 downto 0) := X"01";
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| 29 | constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"02";
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| 30 | constant PACKAGE_HEADER_LENGTH : integer := 22;
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| 31 | constant PACKAGE_END_LENGTH : integer := 2; -- CRC and END-Flag
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| 32 |
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| 33 | constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset
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| 34 |
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| 35 | -- W5300 Registers
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| 36 | constant W5300_BASE_ADR : std_logic_vector (9 downto 0) := (others => '0');
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| 37 | constant W5300_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"0";
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| 38 | constant W5300_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2";
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| 39 | constant W5300_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"4";
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| 40 | constant W5300_SHAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"8";
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| 41 | constant W5300_GAR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"10";
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| 42 | constant W5300_SUBR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"14";
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| 43 | constant W5300_SIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"18";
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| 44 | constant W5300_RTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1C";
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| 45 | constant W5300_RCR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"1E";
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| 46 | constant W5300_TMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"20";
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| 47 | constant W5300_TMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"22";
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| 48 | constant W5300_TMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"24";
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| 49 | constant W5300_TMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"26";
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| 50 | constant W5300_RMS01R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"28";
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| 51 | constant W5300_RMS23R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2A";
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| 52 | constant W5300_RMS45R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2C";
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| 53 | constant W5300_RMS67R : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"2E";
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| 54 | constant W5300_MTYPER : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"30";
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| 55 |
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| 56 | constant W5300_S0_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0";
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| 57 | constant W5300_S0_CR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2";
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| 58 | constant W5300_S0_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4";
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| 59 | constant W5300_S0_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6";
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| 60 | constant W5300_S0_SSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8";
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| 61 | constant W5300_S0_PORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A";
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| 62 | constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12";
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| 63 | constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14";
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| 64 | constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20";
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| 65 | constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24";
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| 66 | constant W5300_S0_RX_RSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28";
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| 67 | constant W5300_S0_TX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E";
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| 68 | constant W5300_S0_RX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30";
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| 69 | -- End W5300 registers
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| 70 |
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| 71 | --
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| 72 | constant W5300_TX_FIFO_SIZE_8B : integer := 15360; -- Socket TX FIFO-Size in Bytes
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| 73 | constant W5300_TX_FIFO_SIZE : integer := (W5300_TX_FIFO_SIZE_8B / 2); -- Socket TX FIFO-Size in 16 Bit Words
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| 74 |
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| 75 | constant RAM_SIZE_64B : integer := 4096;
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| 76 | constant RAM_SIZE_16B : integer := RAM_SIZE_64B * 4;
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| 77 |
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| 78 |
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| 79 |
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| 80 |
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| 81 |
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| 82 | -- TYPE definitions
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| 83 | -- type roi_max_type is array (0 to 8) of std_logic_vector (10 downto 0);
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| 84 | -- type roi_array_type is array (0 to 35) of integer range 0 to 1024;
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| 85 | -- type drs_s_cell_array_type is array (0 to 3) of std_logic_vector (9 downto 0);
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| 86 | -- type adc_data_array_type is array (0 to 3) of std_logic_vector (11 downto 0);
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| 87 |
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| 88 | -- type dac_array_type is array (0 to 7) of integer range 0 to 2**16 - 1;
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| 89 | -- type sensor_array_type is array (0 to 3) of integer range 0 to 2**16 - 1;
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| 90 |
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| 91 | -- constant DEFAULT_ROI : roi_array_type := (115, 125, 100, 102, 155, 101, 0, 101, 106,
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| 92 | -- 181, 121, 189, 101, 101, 187, 56, 187, 101,
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| 93 | -- 2, 141, 101, 100, 10, 100, 178, 101, 174,
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| 94 | -- 12, 181, 100, 102, 101, 102, 0, 101, 108);
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| 95 | -- constant DEFAULT_ROI : roi_array_type := (others => 50);
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| 96 |
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| 97 | -- constant DEFAULT_DAC : dac_array_type := (5001, 5002, 5003, 5004, 5005, 5006, 5007, 5008);
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| 98 | -- constant DEFAULT_DAC : dac_array_type := (others => 0);
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| 99 |
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| 100 | -- Commands
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| 101 | constant CMD_START : std_logic_vector := X"C0";
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| 102 | constant CMD_STOP : std_logic_vector := X"30";
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| 103 | constant CMD_TRIGGER : std_logic_vector := X"A0";
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| 104 | constant CMD_TRIGGER_C : std_logic_vector := X"B0";
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| 105 | constant CMD_TRIGGER_S : std_logic_vector := X"20";
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| 106 | constant CMD_READ : std_logic_vector := X"0A";
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| 107 | constant CMD_WRITE : std_logic_vector := X"05";
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| 108 |
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| 109 | -- DRS Registers
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| 110 | -- constant DRS_WRITE_SHIFT_REG : std_logic_vector := "1101";
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| 111 |
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| 112 | -- Declare functions and procedure
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| 113 |
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| 114 |
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| 115 | end ftm_definitions;
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| 116 |
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| 117 |
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