source: firmware/FTM/test_firmware/FTM_test4/w5300_modul.vhd@ 16318

Last change on this file since 16318 was 10046, checked in by vogler, 15 years ago
Test firmware for FTM hardware testing
  • Property svn:executable set to *
File size: 27.3 KB
Line 
1----------------------------------------------------------------------------------
2-- Company:
3-- Engineer:
4--
5-- Create Date: 11:48:48 11/10/2009
6-- Design Name:
7-- Module Name: w5300_modul - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24library ftm_test4_definitions;
25use ftm_test4_definitions.ftm_definitions.ALL;
26
27---- Uncomment the following library declaration if instantiating
28---- any Xilinx primitives in this code.
29--library UNISIM;
30--use UNISIM.VComponents.all;
31
32ENTITY w5300_modul IS
33 PORT(
34 clk : IN std_logic;
35 wiz_reset : OUT std_logic := '1';
36 addr : OUT std_logic_vector (9 DOWNTO 0);
37 data : INOUT std_logic_vector (15 DOWNTO 0);
38 cs : OUT std_logic := '1';
39 wr : OUT std_logic := '1';
40 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
41 rd : OUT std_logic := '1';
42 int : IN std_logic;
43 write_length : IN std_logic_vector (16 DOWNTO 0);
44 ram_start_addr : IN std_logic_vector (13 DOWNTO 0);
45 ram_data : IN std_logic_vector (15 DOWNTO 0);
46 ram_addr : OUT std_logic_vector (13 DOWNTO 0);
47 data_valid : IN std_logic;
48 data_valid_ack : OUT std_logic := '0';
49 busy : OUT std_logic := '1';
50 write_header_flag, write_end_flag : IN std_logic;
51 fifo_channels : IN std_logic_vector (3 downto 0);
52 s_trigger : OUT std_logic := '0';
53 new_config : OUT std_logic := '0';
54 config_started : in std_logic;
55 config_addr : out std_logic_vector (7 downto 0);
56 config_data : inout std_logic_vector (15 downto 0) := (others => 'Z');
57 config_wr_en : out std_logic := '0';
58 config_rd_en : out std_logic := '0';
59 -- --
60 config_rw_ack, config_rw_ready : in std_logic;
61 -- --
62 config_busy : in std_logic
63 );
64
65-- Declarations
66
67END w5300_modul ;
68
69architecture Behavioral of w5300_modul is
70
71type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
72 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,
73 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA);
74type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2,
75 WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3);
76type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04);
77type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06);
78type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_6, RD_WAIT, RD_WAIT1, RD_END);
79
80signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120";
81
82signal par_addr : std_logic_vector (9 downto 0) := (OTHERS => '0');
83signal par_data : std_logic_vector (15 downto 0) := (OTHERS => '0');
84signal data_read : std_logic_vector (15 downto 0) := (OTHERS => '0');
85signal adc_data_addr : std_logic_vector (13 DOWNTO 0);
86
87signal state_init, next_state , next_state_tmp : state_init_type := RESET;
88signal count : std_logic_vector (2 downto 0) := "000";
89signal state_write : state_write_type := WR_START;
90signal state_interrupt_1 : state_interrupt_1_type := IR1_01;
91signal state_interrupt_2 : state_interrupt_2_type := IR2_01;
92signal state_read_data : state_read_data_type := RD_1;
93
94signal interrupt_ignore : std_logic := '1';
95signal int_flag : std_logic := '0';
96signal ram_access : std_logic := '0';
97
98signal zaehler : std_logic_vector (19 downto 0) := (OTHERS => '0');
99signal data_cnt : integer := 0;
100signal drs_cnt : integer :=0;
101signal channel_cnt : integer range 0 to 9 :=0;
102signal socket_cnt : std_logic_vector (2 downto 0) := "000";
103signal roi_max : std_logic_vector (10 downto 0);
104signal data_end : integer := 0;
105
106signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0');
107signal write_length_bytes : std_logic_vector (16 downto 0);
108
109signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0');
110signal chk_recv_cntr : integer range 0 to 10000 := 0;
111
112-- --
113signal wait_cntr : integer range 0 to 10000 := 0;
114-- --
115
116signal rx_packets_cnt : std_logic_vector (15 downto 0);
117signal next_packet_data : std_logic := '0';
118signal new_config_flag : std_logic := '0';
119
120signal trigger_stop : std_logic := '1';
121
122signal local_write_length : std_logic_vector (16 DOWNTO 0);
123signal local_ram_start_addr : std_logic_vector (13 DOWNTO 0);
124signal local_ram_addr : std_logic_vector (13 downto 0);
125signal local_socket_nr : std_logic_vector (2 DOWNTO 0);
126signal local_write_header_flag, local_write_end_flag : std_logic;
127signal local_fifo_channels : std_logic_vector (3 downto 0);
128
129signal data_valid_int : std_logic := '0';
130
131-- only for debugging
132--signal error_cnt : std_logic_vector (7 downto 0) := (others => '0');
133--signal last_trigger_id : std_logic_vector (15 downto 0) := (others => '0');
134
135
136begin
137
138 --synthesis translate_off
139 RST_TIME <= X"00120";
140 --synthesis translate_on
141
142
143 w5300_init_proc : process (clk, int)
144 begin
145
146 if rising_edge (clk) then
147
148
149 -- Interrupt low
150 if (int = '0') and (interrupt_ignore = '0') then
151 case state_interrupt_1 is
152 when IR1_01 =>
153 int_flag <= '1';
154 busy <= '1';
155 state_interrupt_1 <= IR1_02;
156 when IR1_02 =>
157 state_interrupt_1 <= IR1_03;
158 when IR1_03 =>
159 state_init <= INTERRUPT;
160 socket_cnt <= "000";
161 ram_access <= '0';
162 zaehler <= X"00000";
163 count <= "000";
164 int_flag <= '0';
165 interrupt_ignore <= '1';
166 state_interrupt_1 <= IR1_04;
167 when others =>
168 null;
169 end case;
170 end if; -- int = '0'
171
172 if int_flag = '0' then
173 case state_init is
174 -- Interrupt
175 when INTERRUPT =>
176 case state_interrupt_2 is
177 when IR2_01 =>
178 par_addr <= W5300_IR;
179 state_init <= READ_REG;
180 next_state <= INTERRUPT;
181 state_interrupt_2 <= IR2_02;
182 when IR2_02 =>
183 if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt
184 state_interrupt_2 <= IR2_03;
185 else
186 socket_cnt <= socket_cnt + 1;
187 if (socket_cnt = 7) then
188 state_interrupt_2 <= IR2_06;
189 else
190 state_interrupt_2 <= IR2_02;
191 end if;
192 end if;
193 when IR2_03 =>
194 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register
195 state_init <= READ_REG;
196 next_state <= INTERRUPT;
197 state_interrupt_2 <= IR2_04;
198 when IR2_04 =>
199 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC;
200 par_data <= data_read; -- clear Interrupts
201 state_init <= WRITE_REG;
202 next_state <= INTERRUPT;
203 state_interrupt_2 <= IR2_05;
204 when IR2_05 =>
205 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
206 par_data <= X"0010"; -- CLOSE
207 state_init <= WRITE_REG;
208 next_state <= INTERRUPT;
209 socket_cnt <= socket_cnt + 1;
210 if (socket_cnt = 7) then
211 state_interrupt_2 <= IR2_06;
212 else
213 state_interrupt_2 <= IR2_01;
214 end if;
215
216 when IR2_06 =>
217 state_interrupt_1 <= IR1_01;
218 state_interrupt_2 <= IR2_01;
219 socket_cnt <= "000";
220 state_init <= RESET;
221 end case;
222
223 -- reset W5300
224 when RESET =>
225 busy <= '1';
226 zaehler <= zaehler + 1;
227 wiz_reset <= '0';
228-- led <= X"FF";
229 if (zaehler >= X"00064") then -- wait 2s
230 wiz_reset <= '1';
231 end if;
232 if (zaehler = RST_TIME) then -- wait 10ms
233 zaehler <= X"00000";
234 socket_cnt <= "000";
235 count <= "000";
236 ram_access <= '0';
237 interrupt_ignore <= '0';
238 rd <= '1';
239 wr <= '1';
240 cs <= '1';
241 state_write <= WR_START;
242 state_init <= INIT;
243 end if;
244
245 -- Init
246 when INIT =>
247 par_addr <= W5300_MR;
248 par_data <= X"0000";
249 state_init <= WRITE_REG;
250 next_state <= IM;
251
252 -- Interrupt Mask
253 when IM =>
254 par_addr <= W5300_IMR;
255 par_data <= X"00FF"; -- S0-S7 Interrupts
256 state_init <= WRITE_REG;
257 next_state <= MT;
258
259 -- Memory Type
260 when MT =>
261 par_addr <= W5300_MTYPER;
262 par_data <= X"7FFF"; -- 8K RX, 120K TX-Buffer
263 state_init <= WRITE_REG;
264 next_state <= STX;
265
266 -- Socket TX Memory Size
267 when STX =>
268 par_data <= X"0F0F"; -- 15K TX
269
270 par_addr <= W5300_TMS01R;
271 state_init <=WRITE_REG;
272 next_state <= STX1;
273 when STX1 =>
274 par_addr <= W5300_TMS23R;
275 state_init <=WRITE_REG;
276 next_state <= STX2;
277 when STX2 =>
278 par_addr <= W5300_TMS45R;
279 state_init <=WRITE_REG;
280 next_state <= STX3;
281 when STX3 =>
282 par_addr <= W5300_TMS67R;
283 state_init <=WRITE_REG;
284 next_state <= SRX;
285
286 -- Socket RX Memory Size
287 when SRX =>
288 par_data <= X"0101"; -- 1K RX
289
290 par_addr <= W5300_RMS01R;
291 state_init <=WRITE_REG;
292 next_state <= SRX1;
293 when SRX1 =>
294 par_addr <= W5300_RMS23R;
295 state_init <=WRITE_REG;
296 next_state <= SRX2;
297 when SRX2 =>
298 par_addr <= W5300_RMS45R;
299 state_init <=WRITE_REG;
300 next_state <= SRX3;
301 when SRX3 =>
302 par_addr <= W5300_RMS67R;
303 state_init <=WRITE_REG;
304 next_state <= MAC;
305
306 -- MAC
307 when MAC =>
308 par_addr <= W5300_SHAR;
309 par_data <= MAC_ADDRESS (0);
310 state_init <= WRITE_REG;
311 next_state <= MAC1;
312 when MAC1 =>
313 par_addr <= W5300_SHAR + 2;
314 par_data <= MAC_ADDRESS (1);
315 state_init <= WRITE_REG;
316 next_state <= MAC2;
317 when MAC2 =>
318 par_addr <= W5300_SHAR + 4;
319 par_data <= MAC_ADDRESS (2);
320 state_init <= WRITE_REG;
321 next_state <= GW;
322
323 -- Gateway
324 when GW =>
325 par_addr <= W5300_GAR;
326 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0),8);
327 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1),8);
328 state_init <= WRITE_REG;
329 next_state <= GW1;
330 when GW1 =>
331 par_addr <= W5300_GAR + 2;
332 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2),8);
333 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3),8);
334 state_init <= WRITE_REG;
335 next_state <= SNM;
336
337 -- Subnet Mask
338 when SNM =>
339 par_addr <= W5300_SUBR;
340 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0),8);
341 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1),8);
342 state_init <= WRITE_REG;
343 next_state <= SNM1;
344 when SNM1 =>
345 par_addr <= W5300_SUBR + 2;
346 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2),8);
347 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3),8);
348 state_init <= WRITE_REG;
349 next_state <= IP;
350 -- Own IP-Address
351 when IP =>
352 par_addr <= W5300_SIPR;
353 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0),8);
354 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1),8);
355 state_init <= WRITE_REG;
356 next_state <= IP1;
357 when IP1 =>
358 par_addr <= W5300_SIPR + 2;
359 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2),8);
360 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3),8);
361 state_init <= WRITE_REG;
362 next_state <= SI;
363-- when TIMEOUT =>
364-- par_addr <= W5300_RTR;
365-- par_data <= X"07D0"; -- 0x07D0 = 200ms
366-- state_init <= WRITE_REG;
367-- next_state <= RETRY;
368-- when RETRY =>
369-- par_addr <= W5300_RCR;
370-- par_data <= X"0008";
371-- state_init <= WRITE_REG;
372-- next_state <= SI;
373--
374
375 -- Socket Init
376 when SI =>
377 par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC;
378 par_data <= X"0101"; -- ALIGN, TCP
379 state_init <= WRITE_REG;
380 next_state <= SI1;
381 -- Sx Interrupt Mask
382 when SI1 =>
383 par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC;
384 par_data <= X"000A"; -- TIMEOUT, DISCON
385 state_init <= WRITE_REG;
386 next_state <= SI2;
387 when SI2 =>
388 par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC;
389 par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16);
390 state_init <= WRITE_REG;
391 next_state <= SI3;
392 when SI3 =>
393 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
394 par_data <= X"0001"; -- OPEN
395 state_init <= WRITE_REG;
396 next_state <= SI4;
397 when SI4 =>
398 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
399 state_init <= READ_REG;
400 next_state <= SI5;
401 when SI5 =>
402 if (data_read (7 downto 0) = X"13") then -- is open?
403 state_init <= SI6;
404 else
405 state_init <= SI4;
406 end if;
407 when SI6 =>
408 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
409 par_data <= X"0002"; -- LISTEN
410 state_init <= WRITE_REG;
411 socket_cnt <= socket_cnt + 1;
412 if (socket_cnt = 7) then
413 socket_cnt <= "000";
414 next_state <= ESTABLISH; -- All Sockets open
415 else
416 next_state <= SI; -- Next Socket
417 end if;
418 -- End Socket Init
419
420 when ESTABLISH =>
421 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
422 state_init <= READ_REG;
423 next_state <= EST1;
424 when EST1 =>
425-- led <= data_read (7 downto 0);
426-- led <= X"00";
427 case data_read (7 downto 0) is
428 when X"17" => -- established
429 if (socket_cnt = 7) then
430 socket_cnt <= "000";
431 busy <= '0';
432 state_init <= MAIN;
433 else
434 socket_cnt <= socket_cnt + 1;
435 state_init <= ESTABLISH;
436 end if;
437 when others =>
438 state_init <= ESTABLISH;
439 end case;
440
441 when CONFIG =>
442 new_config <= '1';
443 if (config_started = '1') then
444 new_config <= '0';
445 state_init <= MAIN;
446 end if;
447
448 -- main "loop"
449 when MAIN =>
450 if (trigger_stop = '1') then
451 s_trigger <= '0';
452 end if;
453 data_valid_ack <= '0';
454 state_init <= MAIN1;
455 data_valid_int <= data_valid;
456 when MAIN1 =>
457 if (chk_recv_cntr = 1000) then
458 chk_recv_cntr <= 0;
459 state_read_data <= RD_1;
460 state_init <= READ_DATA;
461 busy <= '1';
462 else
463 chk_recv_cntr <= chk_recv_cntr + 1;
464 state_init <= MAIN2;
465 end if;
466 when MAIN2 =>
467 busy <= '0';
468 if (data_valid = '1') then
469 data_valid_int <= '0';
470 busy <= '1';
471 local_write_length <= write_length;
472 local_ram_start_addr <= ram_start_addr;
473 local_ram_addr <= (others => '0');
474 local_write_header_flag <= write_header_flag;
475 local_write_end_flag <= write_end_flag;
476 local_fifo_channels <= fifo_channels;
477-- data_valid_ack <= '1';
478-- next_state <= MAIN;
479-- state_init <= WRITE_DATA;
480 state_init <= MAIN3;
481 else
482 state_init <= MAIN1;
483 end if;
484 when MAIN3 =>
485-- led <= local_ram_start_addr (7 downto 0);
486 data_valid_ack <= '1';
487 next_state <= MAIN;
488 state_init <= WRITE_DATA;
489
490
491 -- read data from socket 0
492 when READ_DATA =>
493 case state_read_data is
494 when RD_1 =>
495 par_addr <= W5300_S0_RX_RSR;
496 state_init <= READ_REG;
497 next_state <= READ_DATA;
498 state_read_data <= RD_2;
499 when RD_2 =>
500 socket_rx_received (31 downto 16) <= data_read;
501 par_addr <= W5300_S0_RX_RSR + X"2";
502 state_init <= READ_REG;
503 next_state <= READ_DATA;
504 state_read_data <= RD_3;
505 when RD_3 =>
506 socket_rx_received (15 downto 0) <= data_read;
507 state_read_data <= RD_4;
508 when RD_4 =>
509 if (socket_rx_received (16 downto 0) > ('0' & X"000")) then
510 rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2
511 state_read_data <= RD_5;
512 else
513 busy <= '0';
514 state_init <= MAIN;
515 end if;
516 when RD_5 =>
517 if (rx_packets_cnt > 0) then
518 rx_packets_cnt <= rx_packets_cnt - '1';
519 par_addr <= W5300_S0_RX_FIFOR;
520 state_init <= READ_REG;
521 next_state <= READ_DATA;
522 state_read_data <= RD_6;
523 else
524 state_read_data <= RD_END;
525 end if;
526 when RD_6 =>
527 -- read command
528 if (next_packet_data = '0') then
529 case data_read (15 downto 8) is
530 when CMD_TRIGGER =>
531 trigger_stop <= '1';
532 s_trigger <= '1';
533 state_read_data <= RD_5;
534 when CMD_TRIGGER_C =>
535 trigger_stop <= '0';
536 s_trigger <= '1';
537 state_read_data <= RD_5;
538 when CMD_TRIGGER_S =>
539 trigger_stop <= '1';
540 state_read_data <= RD_5;
541 when CMD_WRITE =>
542 next_packet_data <= '1';
543 config_addr <= data_read (7 downto 0);
544 state_read_data <= RD_5;
545 when others =>
546 state_read_data <= RD_5;
547 end case;
548 -- read data
549 else
550 if (config_busy = '0') then
551 config_data <= data_read;
552 config_wr_en <= '1';
553 new_config_flag <= '1';
554 next_packet_data <= '0';
555 state_read_data <= RD_WAIT;
556 end if;
557 end if;
558 when RD_WAIT =>
559 if (config_rw_ack = '1') then
560 state_read_data <= RD_WAIT1;
561 end if;
562 when RD_WAIT1 =>
563 if (config_rw_ready = '1') then
564 config_data <= (others => 'Z');
565 config_wr_en <= '0';
566 state_read_data <= RD_5;
567 end if;
568 when RD_END =>
569 par_addr <= W5300_S0_CR;
570 par_data <= X"0040"; -- RECV
571 state_init <= WRITE_REG;
572 if (new_config_flag = '1') then
573 new_config_flag <= '0';
574 next_state <= CONFIG;
575 else
576 next_state <= MAIN;
577 end if;
578
579 end case; -- state_data_read
580
581
582
583 when WRITE_DATA =>
584 case state_write is
585 when WR_START =>
586 if (local_write_header_flag = '1') then
587 ram_addr <= local_ram_start_addr + 5; -- Address of Trigger-ID (15 downto 0) ????
588 end if;
589 state_write <= WR_WAIT1;
590 when WR_WAIT1 =>
591 state_write <= WR_LENGTH;
592 when WR_LENGTH =>
593 if (local_write_header_flag = '1') then
594 local_socket_nr <= ram_data (2 downto 0);
595-- local_socket_nr <= "000";
596 end if;
597 next_state_tmp <= next_state;
598 write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2)
599 data_cnt <= 0;
600 state_write <= WR_01;
601 -- Check FIFO Size
602 when WR_01 =>
603 par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC;
604 state_init <= READ_REG;
605 next_state <= WRITE_DATA;
606 state_write <= WR_02;
607 when WR_02 =>
608 socket_tx_free (31 downto 16) <= data_read;
609 par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2";
610 state_init <= READ_REG;
611 next_state <= WRITE_DATA;
612 state_write <= WR_03;
613 when WR_03 =>
614 socket_tx_free (15 downto 0) <= data_read;
615 state_write <= WR_04;
616 when WR_04 =>
617
618-- led <= socket_tx_free (15 downto 8);
619
620-- if (socket_tx_free (16 downto 0) < write_length_bytes) then
621 if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then
622 state_write <= WR_01;
623 else
624 if (local_write_header_flag = '1') then
625 state_write <= WR_FIFO;
626 else
627 state_write <= WR_ADC;
628 end if;
629 end if;
630
631 -- Fill FIFO
632
633 -- Write Header
634 when WR_FIFO =>
635 ram_addr <= local_ram_start_addr + local_ram_addr;
636 state_write <= WR_FIFO1;
637 when WR_FIFO1 =>
638 data_cnt <= data_cnt + 1;
639 if (data_cnt < PACKAGE_HEADER_LENGTH) then --???
640 local_ram_addr <= local_ram_addr + 1;
641 if (data_cnt = 2 or data_cnt = 5 or data_cnt = 8 ) then -- skip empty words
642 local_ram_addr <= local_ram_addr + 2;
643 end if;
644 if (data_cnt = 9) then -- skip empty words
645 local_ram_addr <= local_ram_addr + 4;
646 end if;
647 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
648 ram_access <= '1';
649 state_init <= WRITE_REG;
650 next_state <= WRITE_DATA;
651 state_write <= WR_FIFO;
652 else
653 state_write <= WR_ADC;
654 end if;
655 -- End Write Header
656
657 -- Write ADC-Data
658 ---- Start...
659 when WR_ADC =>
660 adc_data_addr <= local_ram_start_addr + local_ram_addr;
661 drs_cnt <= 0;
662 channel_cnt <= 1;
663 data_cnt <= 0;
664 roi_max <= (others => '0');
665 data_end <= 3;
666 state_write <= WR_ADC1;
667
668 ---- Write Channel
669 when WR_ADC1 =>
670 -- read ROI and set end of Channel-Data
671 if (data_cnt = 3) then
672 data_end <= conv_integer (ram_data) + 3;
673 if (ram_data > roi_max) then
674 roi_max <= ram_data (10 downto 0);
675 end if;
676 end if;
677 ram_addr <= adc_data_addr + drs_cnt + (data_cnt * 4);
678 state_write <= WR_ADC2;
679 when WR_ADC2 =>
680 if (data_cnt < data_end) then
681 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
682 ram_access <= '1';
683 state_init <= WRITE_REG;
684 next_state <= WRITE_DATA;
685 data_cnt <= data_cnt + 1;
686 state_write <= WR_ADC1;
687 else
688 -- Next DRS
689 if (drs_cnt < 3) then
690 drs_cnt <= drs_cnt + 1;
691 data_cnt <= 0;
692 data_end <= 3;
693 state_write <= WR_ADC1;
694 else
695 -- Next Channel
696 if (channel_cnt < local_fifo_channels) then
697 channel_cnt <= channel_cnt + 1;
698 roi_max <= (others => '0');
699 drs_cnt <= 0;
700 data_cnt <= 0;
701 data_end <= 3;
702 adc_data_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
703 state_write <= WR_ADC1;
704 else
705 -- Ready
706 if (local_write_end_flag = '1') then
707 state_write <= WR_ENDFLAG;
708 else
709 state_write <= WR_05;
710 end if;
711 end if;
712 end if;
713 end if;
714 -- End Write ADC-Data
715
716 -- Write End Package Flag
717 when WR_ENDFLAG =>
718 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
719 state_write <= WR_ENDFLAG1;
720 when WR_ENDFLAG1 =>
721 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
722 ram_access <= '1';
723 state_init <= WRITE_REG;
724 next_state <= WRITE_DATA;
725 state_write <= WR_ENDFLAG2;
726 when WR_ENDFLAG2 =>
727 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4) + 1;
728 state_write <= WR_ENDFLAG3;
729 when WR_ENDFLAG3 =>
730 state_init <= WRITE_REG;
731 next_state <= WRITE_DATA;
732 state_write <= WR_05a;
733
734 -- End Write End Package Flag
735
736 -- Wait????
737 when WR_05a =>
738 if (wait_cntr < 10) then -- 3000 works???
739 wait_cntr <= wait_cntr + 1;
740 else
741 wait_cntr <= 0;
742 state_write <= WR_05b;
743 end if;
744 when WR_05b =>
745 state_write <= WR_05;
746
747 --Send FIFO
748 when WR_05 =>
749 ram_access <= '0';
750 par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC;
751 par_data <= (0 => write_length_bytes (16), others => '0');
752 state_init <= WRITE_REG;
753 state_write <= WR_06;
754 when WR_06 =>
755 par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2";
756 par_data <= write_length_bytes (15 downto 0);
757 state_init <= WRITE_REG;
758 state_write <= WR_07;
759 when WR_07 =>
760 par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC;
761 par_data <= X"0020"; -- Send
762 state_init <= WRITE_REG;
763 state_write <= WR_08;
764 when others =>
765 state_init <= next_state_tmp;
766 state_write <= WR_START;
767 end case;
768 -- End WRITE_DATA
769
770 when READ_REG =>
771 case count is
772 when "000" =>
773 cs <= '0';
774 rd <= '0';
775 wr <= '1';
776 data <= (others => 'Z'); -- !!!!!!!!!!
777 count <= "001";
778 addr <= par_addr;
779 when "001" =>
780 count <= "010";
781 when "010" =>
782 count <= "100";
783 when "100" =>
784 data_read <= data;
785 count <= "110";
786 when "110" =>
787 count <= "111";
788 when "111" =>
789 cs <= '1';
790 rd <= '1';
791 count <= "000";
792 state_init <= next_state;
793 when others =>
794 null;
795 end case;
796
797 when WRITE_REG =>
798 case count is
799 when "000" =>
800 cs <= '0';
801 wr <= '0';
802 rd <= '1';
803 addr <= par_addr;
804 if (ram_access = '1') then
805 data <= ram_data;
806 else
807 data <= par_data;
808 end if;
809 count <= "100";
810 when "100" =>
811 count <= "101";
812 when "101" =>
813 count <= "110";
814 when "110" =>
815 cs <= '1';
816 wr <= '1';
817 state_init <= next_state;
818 count <= "000";
819 when others =>
820 null;
821 end case;
822
823 when others =>
824 null;
825 end case;
826 end if; -- int_flag = '0'
827
828 end if; -- rising_edge (clk)
829
830 end process w5300_init_proc;
831
832end Behavioral;
833
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