source: firmware/FTM/test_firmware/FTM_test7/FTM_test7.vhd@ 16318

Last change on this file since 16318 was 10046, checked in by vogler, 15 years ago
Test firmware for FTM hardware testing
  • Property svn:executable set to *
File size: 11.3 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 18 October 2010
6-- Design Name:
7-- Module Name: FTM_test5 - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Test firmware for FTM board: RS-485 outputs
12--
13--
14-- Dependencies:
15--
16-- Revision:
17-- Revision 0.01 - File Created
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21
22library IEEE;
23use IEEE.STD_LOGIC_1164.ALL;
24use IEEE.STD_LOGIC_ARITH.ALL;
25use IEEE.STD_LOGIC_UNSIGNED.ALL;
26
27
28Library UNISIM;
29use UNISIM.vcomponents.all;
30
31---- Uncomment the following library declaration if instantiating
32---- any Xilinx primitives in this code.
33--library UNISIM;
34--use UNISIM.VComponents.all;
35
36
37-- library FTM_definitions_test3;
38-- USE FTM_definitions_test3.ftm_array_types.all;
39
40
41
42entity FTM_test7 is
43 port(
44
45
46-- Clock
47 clk : IN STD_LOGIC; -- external clock from
48 -- oscillator U47
49
50-- connection to the WIZnet W5300 ethernet controller
51-- on IO-Bank 1
52-------------------------------------------------------------------------------
53 -- W5300 data bus
54-- W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300
55
56
57 -- W5300 address bus
58-- W_A : out STD_LOGIC_VECTOR(9 downto 1); -- there is NO net W_A0 because
59 -- the W5300 is operated in the
60 -- 16-bit mode
61
62 -- W5300 controll signals
63 -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
64 -- W_CS is also routed to testpoint JP7
65-- W_CS : out STD_LOGIC; -- W5300 chip select
66-- W_INT : IN STD_LOGIC; -- interrupt
67-- W_RD : out STD_LOGIC; -- read
68-- W_WR : out STD_LOGIC; -- write
69-- W_RES : out STD_LOGIC -- reset W5300 chip
70
71 -- W5300 buffer ready indicator
72-- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0);
73
74 -- testpoints (T18) associated with the W5300 on IO-bank 1
75-- W_T : inout STD_LOGIC_VECTOR(3 downto 0);
76
77
78
79-- SPI Interface
80-- connection to the EEPROM U36 (AL25L016M) and
81-- temperature sensors U45, U46, U48 and U49 (all MAX6662)
82-- on IO-Bank 1
83-------------------------------------------------------------------------------
84-- S_CLK : out STD_LOGIC; -- SPI clock
85
86 -- EEPROM
87-- MOSI : out STD_LOGIC; -- master out slave in
88-- MISO : in STD_LOGIC; -- master in slave out
89-- EE_CS : out STD_LOGIC; -- EEPROM chip select
90
91 -- temperature sensors U45, U46, U48 and U49
92-- SIO : inout STD_LOGIC; -- serial IO
93-- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select
94
95
96
97-- Trigger primitives inputs
98-- on IO-Bank 2
99-------------------------------------------------------------------------------
100-- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0
101-- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1
102-- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2
103-- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3
104
105
106
107-- NIM inputs
108------------------------------------------------------------------------------
109 -- on IO-Bank 3
110-- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input
111-- Veto : in STD_LOGIC; -- trigger veto input
112-- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs
113
114 -- on IO-Bank 0
115-- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available
116
117
118
119-- LEDs on IO-Banks 0 and 3
120-------------------------------------------------------------------------------
121-- LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red
122-- LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow
123-- LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green
124
125
126
127-- Clock conditioner LMK03000
128-- on IO-Bank 3
129-------------------------------------------------------------------------------
130-- CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock
131-- LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable
132-- DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data
133
134-- SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization
135-- LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect
136
137
138
139
140-- various RS-485 Interfaces
141-- on IO-Bank 3
142-------------------------------------------------------------------------------
143 -- Bus 1: FTU slow control
144 Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable
145 Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable
146
147-- Bus1_RxD_0 : in STD_LOGIC; -- crate 0
148 Bus1_TxD_0 : out STD_LOGIC;
149
150-- Bus1_RxD_1 : in STD_LOGIC; -- crate 1
151 Bus1_TxD_1 : out STD_LOGIC;
152
153-- Bus1_RxD_2 : in STD_LOGIC; -- crate 2
154 Bus1_TxD_2 : out STD_LOGIC;
155
156-- Bus1_RxD_3 : in STD_LOGIC; -- crate 3
157 Bus1_TxD_3 : out STD_LOGIC;
158
159
160 -- Bus 2: Trigger-ID to FAD boards
161 Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable
162 Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable
163
164-- Bus2_RxD_0 : in STD_LOGIC; -- crate 0
165 Bus2_TxD_0 : out STD_LOGIC;
166
167-- Bus2_RxD_1 : in STD_LOGIC; -- crate 1
168 Bus2_TxD_1 : out STD_LOGIC;
169
170-- Bus2_RxD_2 : in STD_LOGIC; -- crate 2
171 Bus2_TxD_2 : out STD_LOGIC;
172
173-- Bus2_RxD_3 : in STD_LOGIC; -- crate 3
174 Bus2_TxD_3 : out STD_LOGIC;
175
176
177-- auxiliary access
178-- Aux_Rx_D : in STD_LOGIC; --
179 Aux_Tx_D : out STD_LOGIC; --
180 Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable
181 Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID
182
183
184-- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
185-- TrID_Rx_D : in STD_LOGIC; --
186 TrID_Tx_D : out STD_LOGIC --
187
188
189-- Crate-Resets
190-- on IO-Bank 3
191-------------------------------------------------------------------------------
192-- Crate_Res0 : out STD_LOGIC; --
193-- Crate_Res1 : out STD_LOGIC; --
194-- Crate_Res2 : out STD_LOGIC; --
195-- Crate_Res3 : out STD_LOGIC; --
196
197
198-- Busy signals from the FAD boards
199-- on IO-Bank 3
200-------------------------------------------------------------------------------
201-- Busy0 : in STD_LOGIC; --
202-- Busy1 : in STD_LOGIC; --
203-- Busy2 : in STD_LOGIC; --
204-- Busy3 : in STD_LOGIC; --
205
206
207
208-- NIM outputs
209-- on IO-Bank 0
210-- LVDS output at the FPGA followed by LVDS to NIM conversion stage
211-------------------------------------------------------------------------------
212-- calibration
213-- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+
214-- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1-
215-- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+
216-- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2-
217
218-- auxiliarry / spare NIM outputs
219-- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+
220-- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0-
221-- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+
222-- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1-
223
224
225
226-- fast control signal outputs
227-- LVDS output at the FPGA followed by LVDS to NIM conversion stage
228-- conversion stage
229-------------------------------------------------------------------------------
230-- RES_p : out STD_LOGIC; -- RES+ Reset
231-- RES_n : out STD_LOGIC; -- RES- IO-Bank 0
232
233-- TRG_p : out STD_LOGIC; -- TRG+ Trigger
234-- TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0
235
236-- TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker
237-- TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2
238-- TIM_Sel : out STD_LOGIC -- Time Marker selector on
239 -- IO-Bank 2
240
241-- CLD_FPGA : out STD_LOGIC; -- DRS-Clock feedback into FPGA
242
243
244
245-- LVDS calibration outputs
246-- on IO-Bank 0
247-------------------------------------------------------------------------------
248-- to connector J13
249-- Cal_0_p : out STD_LOGIC;
250-- Cal_0_n : out STD_LOGIC;
251-- Cal_1_p : out STD_LOGIC;
252-- Cal_1_n : out STD_LOGIC;
253-- Cal_2_p : out STD_LOGIC;
254-- Cal_2_n : out STD_LOGIC;
255-- Cal_3_p : out STD_LOGIC;
256-- Cal_3_n : out STD_LOGIC;
257
258-- to connector J12
259-- Cal_4_p : out STD_LOGIC;
260-- Cal_4_n : out STD_LOGIC;
261-- Cal_5_p : out STD_LOGIC;
262-- Cal_5_n : out STD_LOGIC;
263-- Cal_6_p : out STD_LOGIC;
264-- Cal_6_n : out STD_LOGIC;
265-- Cal_7_p : out STD_LOGIC;
266-- Cal_7_n : out STD_LOGIC;
267
268
269-- Testpoints
270-------------------------------------------------------------------------------
271-- TP : inout STD_LOGIC_VECTOR(32 downto 0)
272-- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only
273
274-- Board ID - inputs
275-- local board-ID "solder programmable"
276-- all on 'input only' pins
277-------------------------------------------------------------------------------
278-- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only
279 );
280end FTM_test7;
281
282
283architecture Behavioral of FTM_test7 is
284
285COMPONENT FTM_Test7_dcm
286 PORT(
287 CLKIN_IN : IN std_logic;
288 CLKFX_OUT : OUT std_logic;
289 CLKIN_IBUFG_OUT : OUT std_logic;
290 CLK0_OUT : OUT std_logic;
291 LOCKED_OUT : OUT std_logic
292 );
293 END COMPONENT;
294
295
296 component Clock_Divider
297 port(
298 clock_in : IN STD_LOGIC;
299 clock_out : OUT STD_LOGIC
300 );
301 end component;
302
303
304signal clk_50k_sig : std_logic;
305signal clk_5M_sig : std_logic;
306
307
308
309begin
310
311 Bus1_TxD_0 <= clk_50k_sig;
312 Bus1_TxD_1 <= clk_50k_sig;
313 Bus1_TxD_2 <= clk_50k_sig;
314 Bus1_TxD_3 <= clk_50k_sig;
315
316 Bus2_TxD_0 <= clk_50k_sig;
317 Bus2_TxD_1 <= clk_50k_sig;
318 Bus2_TxD_2 <= clk_50k_sig;
319 Bus2_TxD_3 <= clk_50k_sig;
320
321 Aux_Tx_D <= clk_50k_sig;
322 TrID_Tx_D <= clk_50k_sig;
323
324 Bus1_Tx_En <= '1';
325 Bus1_Rx_En <= '1';
326 Bus2_Tx_En <= '1';
327 Bus2_Rx_En <= '1';
328 Aux_Rx_En <= '1';
329 Aux_Tx_En <= '1';
330
331
332 Inst_FTM_Test7_dcm: FTM_Test7_dcm PORT MAP(
333 CLKIN_IN => clk,
334 CLKFX_OUT => clk_5M_sig,
335 CLKIN_IBUFG_OUT => open,
336 CLK0_OUT => open,
337 LOCKED_OUT => open
338 );
339
340 Inst_Clock_Divider : Clock_Divider
341 port map (
342 clock_in => clk_5M_sig,
343 clock_out => clk_50k_sig
344 );
345
346end Behavioral;
347
348
349
350library IEEE;
351use IEEE.STD_LOGIC_1164.ALL;
352use IEEE.STD_LOGIC_ARITH.ALL;
353use IEEE.STD_LOGIC_UNSIGNED.ALL;
354
355entity Clock_Divider is
356 port(
357 clock_in : in std_logic;
358 clock_out : out std_logic
359 );
360end entity Clock_Divider;
361
362architecture RTL of Clock_Divider is
363
364 constant max_count : integer := 5000000/50000; -- for implementation
365
366begin
367
368 process(clock_in)
369 variable count : integer range 0 to max_count;
370 begin
371 if rising_edge(clock_in) then
372 if count < max_count/2 then
373 clock_out <= '0';
374 count := count + 1;
375 elsif count < max_count then
376 clock_out <= '1';
377 count := count + 1;
378 else
379 count := 0;
380 clock_out <= '0';
381 end if;
382 end if;
383 end process;
384
385end architecture RTL;
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