source: firmware/FTM/test_firmware/FTM_test8/FTM_test8.vhd@ 17497

Last change on this file since 17497 was 10058, checked in by weitzel, 15 years ago
Some modifications and a test bench for FTM_test8
  • Property svn:executable set to *
File size: 15.1 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 21 October 2010
6-- Design Name:
7-- Module Name: FTM_test8 - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Test firmware for FTM board: test a RS-485 input
12--
13--
14-- Dependencies:
15--
16-- Revision:
17-- Revision 0.01 - File Created
18-- Revision 0.02 - Some modifications, November 15, 2010, Q. Weitzel
19-- Additional Comments:
20--
21----------------------------------------------------------------------------------
22
23library IEEE;
24use IEEE.STD_LOGIC_1164.ALL;
25use IEEE.STD_LOGIC_ARITH.ALL;
26use IEEE.STD_LOGIC_UNSIGNED.ALL;
27
28Library UNISIM;
29use UNISIM.vcomponents.all;
30
31---- Uncomment the following library declaration if instantiating
32---- any Xilinx primitives in this code.
33--library UNISIM;
34--use UNISIM.VComponents.all;
35
36-- library FTM_definitions_test3;
37-- USE FTM_definitions_test3.ftm_array_types.all;
38
39entity FTM_test8 is
40 port(
41
42-- Clock
43 clk : IN STD_LOGIC; -- external clock from
44 -- oscillator U47
45-- connection to the WIZnet W5300 ethernet controller
46-- on IO-Bank 1
47-------------------------------------------------------------------------------
48 -- W5300 data bus
49-- W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300
50
51
52 -- W5300 address bus
53-- W_A : out STD_LOGIC_VECTOR(9 downto 1); -- there is NO net W_A0 because
54 -- the W5300 is operated in the
55 -- 16-bit mode
56
57 -- W5300 controll signals
58 -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
59 -- W_CS is also routed to testpoint JP7
60-- W_CS : out STD_LOGIC; -- W5300 chip select
61-- W_INT : IN STD_LOGIC; -- interrupt
62-- W_RD : out STD_LOGIC; -- read
63-- W_WR : out STD_LOGIC; -- write
64-- W_RES : out STD_LOGIC -- reset W5300 chip
65
66 -- W5300 buffer ready indicator
67-- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0);
68
69 -- testpoints (T18) associated with the W5300 on IO-bank 1
70-- W_T : inout STD_LOGIC_VECTOR(3 downto 0);
71
72
73
74-- SPI Interface
75-- connection to the EEPROM U36 (AL25L016M) and
76-- temperature sensors U45, U46, U48 and U49 (all MAX6662)
77-- on IO-Bank 1
78-------------------------------------------------------------------------------
79-- S_CLK : out STD_LOGIC; -- SPI clock
80
81 -- EEPROM
82-- MOSI : out STD_LOGIC; -- master out slave in
83-- MISO : in STD_LOGIC; -- master in slave out
84-- EE_CS : out STD_LOGIC; -- EEPROM chip select
85
86 -- temperature sensors U45, U46, U48 and U49
87-- SIO : inout STD_LOGIC; -- serial IO
88-- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select
89
90
91
92-- Trigger primitives inputs
93-- on IO-Bank 2
94-------------------------------------------------------------------------------
95-- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0
96-- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1
97-- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2
98-- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3
99
100
101
102-- NIM inputs
103------------------------------------------------------------------------------
104 -- on IO-Bank 3
105-- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input
106-- Veto : in STD_LOGIC; -- trigger veto input
107-- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs
108
109 -- on IO-Bank 0
110-- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available
111
112
113
114-- LEDs on IO-Banks 0 and 3
115-------------------------------------------------------------------------------
116 LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red
117 LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow
118 LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green
119
120-- Clock conditioner LMK03000
121-- on IO-Bank 3
122-------------------------------------------------------------------------------
123-- CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock
124-- LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable
125-- DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data
126
127-- SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization
128-- LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect
129
130-- various RS-485 Interfaces
131-- on IO-Bank 3
132-------------------------------------------------------------------------------
133 -- Bus 1: FTU slow control
134 Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable
135 Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable
136
137 Bus1_RxD_0 : in STD_LOGIC; -- crate 0
138 Bus1_TxD_0 : out STD_LOGIC
139
140-- Bus1_RxD_1 : in STD_LOGIC; -- crate 1
141-- Bus1_TxD_1 : out STD_LOGIC;
142
143-- Bus1_RxD_2 : in STD_LOGIC; -- crate 2
144-- Bus1_TxD_2 : out STD_LOGIC;
145
146-- Bus1_RxD_3 : in STD_LOGIC; -- crate 3
147-- Bus1_TxD_3 : out STD_LOGIC;
148
149
150 -- Bus 2: Trigger-ID to FAD boards
151-- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable
152-- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable
153
154-- Bus2_RxD_0 : in STD_LOGIC; -- crate 0
155-- Bus2_TxD_0 : out STD_LOGIC;
156
157-- Bus2_RxD_1 : in STD_LOGIC; -- crate 1
158-- Bus2_TxD_1 : out STD_LOGIC;
159
160-- Bus2_RxD_2 : in STD_LOGIC; -- crate 2
161-- Bus2_TxD_2 : out STD_LOGIC;
162
163-- Bus2_RxD_3 : in STD_LOGIC; -- crate 3
164-- Bus2_TxD_3 : out STD_LOGIC;
165
166
167-- auxiliary access
168-- Aux_Rx_D : in STD_LOGIC; --
169-- Aux_Tx_D : out STD_LOGIC; --
170-- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable
171-- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID
172
173
174-- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
175-- TrID_Rx_D : in STD_LOGIC; --
176-- TrID_Tx_D : out STD_LOGIC --
177
178
179-- Crate-Resets
180-- on IO-Bank 3
181-------------------------------------------------------------------------------
182-- Crate_Res0 : out STD_LOGIC; --
183-- Crate_Res1 : out STD_LOGIC; --
184-- Crate_Res2 : out STD_LOGIC; --
185-- Crate_Res3 : out STD_LOGIC; --
186
187
188-- Busy signals from the FAD boards
189-- on IO-Bank 3
190-------------------------------------------------------------------------------
191-- Busy0 : in STD_LOGIC; --
192-- Busy1 : in STD_LOGIC; --
193-- Busy2 : in STD_LOGIC; --
194-- Busy3 : in STD_LOGIC; --
195
196
197
198-- NIM outputs
199-- on IO-Bank 0
200-- LVDS output at the FPGA followed by LVDS to NIM conversion stage
201-------------------------------------------------------------------------------
202-- calibration
203-- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+
204-- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1-
205-- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+
206-- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2-
207
208-- auxiliarry / spare NIM outputs
209-- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+
210-- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0-
211-- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+
212-- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1-
213
214
215
216-- fast control signal outputs
217-- LVDS output at the FPGA followed by LVDS to NIM conversion stage
218-- conversion stage
219-------------------------------------------------------------------------------
220-- RES_p : out STD_LOGIC; -- RES+ Reset
221-- RES_n : out STD_LOGIC; -- RES- IO-Bank 0
222
223-- TRG_p : out STD_LOGIC; -- TRG+ Trigger
224-- TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0
225
226-- TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker
227-- TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2
228-- TIM_Sel : out STD_LOGIC -- Time Marker selector on
229 -- IO-Bank 2
230
231-- CLD_FPGA : out STD_LOGIC; -- DRS-Clock feedback into FPGA
232
233
234
235-- LVDS calibration outputs
236-- on IO-Bank 0
237-------------------------------------------------------------------------------
238-- to connector J13
239-- Cal_0_p : out STD_LOGIC;
240-- Cal_0_n : out STD_LOGIC;
241-- Cal_1_p : out STD_LOGIC;
242-- Cal_1_n : out STD_LOGIC;
243-- Cal_2_p : out STD_LOGIC;
244-- Cal_2_n : out STD_LOGIC;
245-- Cal_3_p : out STD_LOGIC;
246-- Cal_3_n : out STD_LOGIC;
247
248-- to connector J12
249-- Cal_4_p : out STD_LOGIC;
250-- Cal_4_n : out STD_LOGIC;
251-- Cal_5_p : out STD_LOGIC;
252-- Cal_5_n : out STD_LOGIC;
253-- Cal_6_p : out STD_LOGIC;
254-- Cal_6_n : out STD_LOGIC;
255-- Cal_7_p : out STD_LOGIC;
256-- Cal_7_n : out STD_LOGIC;
257
258
259-- Testpoints
260-------------------------------------------------------------------------------
261-- TP : inout STD_LOGIC_VECTOR(32 downto 0)
262-- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only
263
264-- Board ID - inputs
265-- local board-ID "solder programmable"
266-- all on 'input only' pins
267-------------------------------------------------------------------------------
268-- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only
269 );
270end FTM_test8;
271
272architecture Behavioral of FTM_test8 is
273
274 COMPONENT FTM_Test8_dcm
275 PORT(
276 CLKIN_IN : IN std_logic;
277 RST_IN : IN std_logic;
278 CLKFX_OUT : OUT std_logic;
279 CLK0_OUT : OUT std_logic;
280 LOCKED_OUT : OUT std_logic
281 );
282 END COMPONENT;
283
284 component FTM_test8_rs485_interface
285 GENERIC(
286 CLOCK_FREQUENCY : integer; -- Hertz
287 BAUD_RATE : integer -- bits / sec
288 );
289 PORT(
290 clk : IN std_logic;
291 -- RS485
292 rx_d : IN std_logic;
293 rx_en : OUT std_logic;
294 tx_d : OUT std_logic;
295 tx_en : OUT std_logic;
296 -- FPGA
297 rx_data : OUT std_logic_vector(7 DOWNTO 0);
298 -- rx_busy : OUT std_logic := '0';
299 rx_valid : OUT std_logic := '0';
300 tx_data : IN std_logic_vector(7 DOWNTO 0);
301 tx_busy : OUT std_logic := '0';
302 tx_start : IN std_logic
303 );
304 end component;
305
306 signal reset_sig : STD_LOGIC := '0'; -- initialize reset to 0 at power up
307 signal clk_50M_sig : STD_LOGIC;
308
309 -- signal enable_sig : enable_array_type := DEFAULT_ENABLE;
310
311 signal rx_en_sig : STD_LOGIC := '0';
312 signal tx_en_sig : STD_LOGIC := '0';
313 signal rx_sig : STD_LOGIC;
314 signal tx_sig : STD_LOGIC := 'X';
315 signal rx_data_sig : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
316 -- signal rx_busy_sig : STD_LOGIC;
317 signal rx_valid_sig : STD_LOGIC;
318
319 type FTM_test8_StateType is (INIT, RUN1, RUN2, RUN3, RUN4);
320 signal FTM_test8_State, FTM_test8_NextState: FTM_test8_StateType;
321
322begin
323
324 Inst_FTM_Test8_dcm: FTM_Test8_dcm PORT MAP(
325 CLKIN_IN => clk,
326 RST_IN => reset_sig,
327 CLKFX_OUT => clk_50M_sig,
328 CLK0_OUT => open,
329 LOCKED_OUT => open
330 );
331
332 Inst_FTM_test8_rs485_interface : FTM_test8_rs485_interface
333 generic map(
334 CLOCK_FREQUENCY => 50000000,
335 -- BAUD_RATE => 10000000 --simulation
336 BAUD_RATE => 250000 --implement
337 )
338 port map(
339 clk => clk_50M_sig,
340 -- RS485
341 rx_d => rx_sig,
342 rx_en => rx_en_sig,
343 tx_d => tx_sig,
344 tx_en => tx_en_sig,
345 -- FPGA
346 rx_data => rx_data_sig,
347 -- rx_busy => rx_busy_sig,
348 rx_valid => rx_valid_sig,
349 tx_data => (others => '0'),
350 tx_busy => open,
351 tx_start => '0'
352 );
353
354 Bus1_Rx_En <= rx_en_sig;
355 Bus1_Tx_En <= tx_en_sig;
356 Bus1_TxD_0 <= tx_sig;
357 rx_sig <= Bus1_RxD_0;
358
359 --FTM main state machine (two-process implementation)
360
361 FTM_test8_Registers: process (clk_50M_sig)
362 begin
363 if Rising_edge(clk_50M_sig) then
364 FTM_test8_State <= FTM_test8_NextState;
365 end if;
366 end process FTM_test8_Registers;
367
368 FTM_test8_C_logic: process (FTM_test8_State, rx_data_sig, rx_valid_sig)
369 begin
370 FTM_test8_NextState <= FTM_test8_State;
371 case FTM_test8_State is
372 when INIT =>
373 reset_sig <= '0';
374 LED_red <= "0000";
375 if (rx_data_sig = "00110001" and rx_valid_sig = '1') then
376 FTM_test8_NextState <= RUN1;
377 elsif (rx_data_sig = "00110010" and rx_valid_sig = '1') then
378 FTM_test8_NextState <= RUN2;
379 elsif (rx_data_sig = "00110011" and rx_valid_sig = '1') then
380 FTM_test8_NextState <= RUN3;
381 elsif (rx_data_sig = "00110100" and rx_valid_sig = '1') then
382 FTM_test8_NextState <= RUN4;
383 else
384 FTM_test8_NextState <= INIT;
385 end if;
386 when RUN1 =>
387 reset_sig <= '0';
388 LED_red <= "0001";
389 if (rx_data_sig = "00110000" and rx_valid_sig = '1') then
390 FTM_test8_NextState <= INIT;
391 elsif (rx_data_sig = "00110010" and rx_valid_sig = '1') then
392 FTM_test8_NextState <= RUN2;
393 elsif (rx_data_sig = "00110011" and rx_valid_sig = '1') then
394 FTM_test8_NextState <= RUN3;
395 elsif (rx_data_sig = "00110100" and rx_valid_sig = '1') then
396 FTM_test8_NextState <= RUN4;
397 else
398 FTM_test8_NextState <= RUN1;
399 end if;
400 when RUN2 =>
401 reset_sig <= '0';
402 LED_red <= "0010";
403 if (rx_data_sig = "00110000" and rx_valid_sig = '1') then
404 FTM_test8_NextState <= INIT;
405 elsif (rx_data_sig = "00110001" and rx_valid_sig = '1') then
406 FTM_test8_NextState <= RUN1;
407 elsif (rx_data_sig = "00110011" and rx_valid_sig = '1') then
408 FTM_test8_NextState <= RUN3;
409 elsif (rx_data_sig = "00110100" and rx_valid_sig = '1') then
410 FTM_test8_NextState <= RUN4;
411 else
412 FTM_test8_NextState <= RUN2;
413 end if;
414 when RUN3 =>
415 reset_sig <= '0';
416 LED_red <= "0100";
417 if (rx_data_sig = "00110000" and rx_valid_sig = '1') then
418 FTM_test8_NextState <= INIT;
419 elsif (rx_data_sig = "00110001" and rx_valid_sig = '1') then
420 FTM_test8_NextState <= RUN1;
421 elsif (rx_data_sig = "00110010" and rx_valid_sig = '1') then
422 FTM_test8_NextState <= RUN2;
423 elsif (rx_data_sig = "00110100" and rx_valid_sig = '1') then
424 FTM_test8_NextState <= RUN4;
425 else
426 FTM_test8_NextState <= RUN3;
427 end if;
428 when RUN4 =>
429 reset_sig <= '0';
430 LED_red <= "1000";
431 if (rx_data_sig = "00110000" and rx_valid_sig = '1') then
432 FTM_test8_NextState <= INIT;
433 elsif (rx_data_sig = "00110001" and rx_valid_sig = '1') then
434 FTM_test8_NextState <= RUN1;
435 elsif (rx_data_sig = "00110010" and rx_valid_sig = '1') then
436 FTM_test8_NextState <= RUN2;
437 elsif (rx_data_sig = "00110011" and rx_valid_sig = '1') then
438 FTM_test8_NextState <= RUN3;
439 else
440 FTM_test8_NextState <= RUN4;
441 end if;
442 end case;
443 end process FTM_test8_C_logic;
444
445 LED_ye <= "11";
446 LED_gn <= "11";
447
448end Behavioral;
449
450
451
452
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