source: firmware/FTM/test_firmware/FTM_test9/FTM_test9.vhd@ 10104

Last change on this file since 10104 was 10104, checked in by weitzel, 12 years ago
FTM_test9 added: check FTM-FTU communication
File size: 16.9 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 13 January 2011
6-- Design Name:
7-- Module Name: FTM_test9 - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Test firmware for FTM board: try to contact FTU via RS485
12--
13--
14-- Dependencies:
15--
16-- Revision:
17-- Revision 0.01 - File Created
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21
22library IEEE;
23use IEEE.STD_LOGIC_1164.ALL;
24use IEEE.STD_LOGIC_ARITH.ALL;
25use IEEE.STD_LOGIC_UNSIGNED.ALL;
26
27---- Uncomment the following library declaration if instantiating
28---- any Xilinx primitives in this code.
29library UNISIM;
30use UNISIM.VComponents.all;
31
32entity FTM_test9 is
33 port(
34
35-- Clock
36 clk : IN STD_LOGIC; -- external clock from
37 -- oscillator U47
38-- connection to the WIZnet W5300 ethernet controller
39-- on IO-Bank 1
40-------------------------------------------------------------------------------
41 -- W5300 data bus
42-- W_D : inout STD_LOGIC_VECTOR(15 downto 0); -- 16-bit data bus to W5300
43
44
45 -- W5300 address bus
46-- W_A : out STD_LOGIC_VECTOR(9 downto 1); -- there is NO net W_A0 because
47 -- the W5300 is operated in the
48 -- 16-bit mode
49
50 -- W5300 controll signals
51 -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
52 -- W_CS is also routed to testpoint JP7
53-- W_CS : out STD_LOGIC; -- W5300 chip select
54-- W_INT : IN STD_LOGIC; -- interrupt
55-- W_RD : out STD_LOGIC; -- read
56-- W_WR : out STD_LOGIC; -- write
57-- W_RES : out STD_LOGIC -- reset W5300 chip
58
59 -- W5300 buffer ready indicator
60-- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0);
61
62 -- testpoints (T18) associated with the W5300 on IO-bank 1
63-- W_T : inout STD_LOGIC_VECTOR(3 downto 0);
64
65
66
67-- SPI Interface
68-- connection to the EEPROM U36 (AL25L016M) and
69-- temperature sensors U45, U46, U48 and U49 (all MAX6662)
70-- on IO-Bank 1
71-------------------------------------------------------------------------------
72-- S_CLK : out STD_LOGIC; -- SPI clock
73
74 -- EEPROM
75-- MOSI : out STD_LOGIC; -- master out slave in
76-- MISO : in STD_LOGIC; -- master in slave out
77-- EE_CS : out STD_LOGIC; -- EEPROM chip select
78
79 -- temperature sensors U45, U46, U48 and U49
80-- SIO : inout STD_LOGIC; -- serial IO
81-- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select
82
83
84
85-- Trigger primitives inputs
86-- on IO-Bank 2
87-------------------------------------------------------------------------------
88-- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0
89-- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1
90-- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2
91-- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3
92
93
94
95-- NIM inputs
96------------------------------------------------------------------------------
97 -- on IO-Bank 3
98-- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input
99-- Veto : in STD_LOGIC; -- trigger veto input
100-- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs
101
102 -- on IO-Bank 0
103-- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available
104
105
106
107-- LEDs on IO-Banks 0 and 3
108-------------------------------------------------------------------------------
109 LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red
110 LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow
111 LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green
112
113-- Clock conditioner LMK03000
114-- on IO-Bank 3
115-------------------------------------------------------------------------------
116-- CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock
117-- LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable
118-- DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data
119
120-- SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization
121-- LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect
122
123-- various RS-485 Interfaces
124-- on IO-Bank 3
125-------------------------------------------------------------------------------
126 -- Bus 1: FTU slow control
127 Bus1_Tx_En : out STD_LOGIC; -- bus 1: transmitter enable
128 Bus1_Rx_En : out STD_LOGIC; -- bus 1: receiver enable
129
130 Bus1_RxD_0 : in STD_LOGIC; -- crate 0
131 Bus1_TxD_0 : out STD_LOGIC
132
133-- Bus1_RxD_1 : in STD_LOGIC; -- crate 1
134-- Bus1_TxD_1 : out STD_LOGIC;
135
136-- Bus1_RxD_2 : in STD_LOGIC; -- crate 2
137-- Bus1_TxD_2 : out STD_LOGIC;
138
139-- Bus1_RxD_3 : in STD_LOGIC; -- crate 3
140-- Bus1_TxD_3 : out STD_LOGIC;
141
142
143 -- Bus 2: Trigger-ID to FAD boards
144-- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable
145-- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable
146
147-- Bus2_RxD_0 : in STD_LOGIC; -- crate 0
148-- Bus2_TxD_0 : out STD_LOGIC;
149
150-- Bus2_RxD_1 : in STD_LOGIC; -- crate 1
151-- Bus2_TxD_1 : out STD_LOGIC;
152
153-- Bus2_RxD_2 : in STD_LOGIC; -- crate 2
154-- Bus2_TxD_2 : out STD_LOGIC;
155
156-- Bus2_RxD_3 : in STD_LOGIC; -- crate 3
157-- Bus2_TxD_3 : out STD_LOGIC;
158
159
160-- auxiliary access
161-- Aux_Rx_D : in STD_LOGIC; --
162-- Aux_Tx_D : out STD_LOGIC; --
163-- Aux_Rx_En : out STD_LOGIC; -- Rx- and Tx enable
164-- Aux_Tx_En : out STD_LOGIC; -- also for auxiliary Trigger-ID
165
166
167-- auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
168-- TrID_Rx_D : in STD_LOGIC; --
169-- TrID_Tx_D : out STD_LOGIC --
170
171
172-- Crate-Resets
173-- on IO-Bank 3
174-------------------------------------------------------------------------------
175-- Crate_Res0 : out STD_LOGIC; --
176-- Crate_Res1 : out STD_LOGIC; --
177-- Crate_Res2 : out STD_LOGIC; --
178-- Crate_Res3 : out STD_LOGIC; --
179
180
181-- Busy signals from the FAD boards
182-- on IO-Bank 3
183-------------------------------------------------------------------------------
184-- Busy0 : in STD_LOGIC; --
185-- Busy1 : in STD_LOGIC; --
186-- Busy2 : in STD_LOGIC; --
187-- Busy3 : in STD_LOGIC; --
188
189
190
191-- NIM outputs
192-- on IO-Bank 0
193-- LVDS output at the FPGA followed by LVDS to NIM conversion stage
194-------------------------------------------------------------------------------
195-- calibration
196-- Cal_NIM1_p : out STD_LOGIC; -- Cal_NIM1+
197-- Cal_NIM1_n : out STD_LOGIC; -- Cal_NIM1-
198-- Cal_NIM2_p : out STD_LOGIC; -- Cal_NIM2+
199-- Cal_NIM2_n : out STD_LOGIC; -- Cal_NIM2-
200
201-- auxiliarry / spare NIM outputs
202-- NIM_Out0_p : out STD_LOGIC; -- NIM_Out0+
203-- NIM_Out0_n : out STD_LOGIC; -- NIM_Out0-
204-- NIM_Out1_p : out STD_LOGIC; -- NIM_Out1+
205-- NIM_Out1_n : out STD_LOGIC; -- NIM_Out1-
206
207
208
209-- fast control signal outputs
210-- LVDS output at the FPGA followed by LVDS to NIM conversion stage
211-- conversion stage
212-------------------------------------------------------------------------------
213-- RES_p : out STD_LOGIC; -- RES+ Reset
214-- RES_n : out STD_LOGIC; -- RES- IO-Bank 0
215
216-- TRG_p : out STD_LOGIC; -- TRG+ Trigger
217-- TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0
218
219-- TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker
220-- TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2
221-- TIM_Sel : out STD_LOGIC -- Time Marker selector on
222 -- IO-Bank 2
223
224-- CLD_FPGA : out STD_LOGIC; -- DRS-Clock feedback into FPGA
225
226
227
228-- LVDS calibration outputs
229-- on IO-Bank 0
230-------------------------------------------------------------------------------
231-- to connector J13
232-- Cal_0_p : out STD_LOGIC;
233-- Cal_0_n : out STD_LOGIC;
234-- Cal_1_p : out STD_LOGIC;
235-- Cal_1_n : out STD_LOGIC;
236-- Cal_2_p : out STD_LOGIC;
237-- Cal_2_n : out STD_LOGIC;
238-- Cal_3_p : out STD_LOGIC;
239-- Cal_3_n : out STD_LOGIC;
240
241-- to connector J12
242-- Cal_4_p : out STD_LOGIC;
243-- Cal_4_n : out STD_LOGIC;
244-- Cal_5_p : out STD_LOGIC;
245-- Cal_5_n : out STD_LOGIC;
246-- Cal_6_p : out STD_LOGIC;
247-- Cal_6_n : out STD_LOGIC;
248-- Cal_7_p : out STD_LOGIC;
249-- Cal_7_n : out STD_LOGIC;
250
251
252-- Testpoints
253-------------------------------------------------------------------------------
254-- TP : inout STD_LOGIC_VECTOR(32 downto 0)
255-- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only
256
257-- Board ID - inputs
258-- local board-ID "solder programmable"
259-- all on 'input only' pins
260-------------------------------------------------------------------------------
261-- brd_id : in STD_LOGIC_VECTOR(7 downto 0) -- input only
262 );
263end FTM_test9;
264
265architecture Behavioral of FTM_test9 is
266
267 COMPONENT FTM_test9_dcm
268 PORT(
269 CLKIN_IN : IN std_logic;
270 RST_IN : IN std_logic;
271 CLKFX_OUT : OUT std_logic;
272 CLK0_OUT : OUT std_logic;
273 LOCKED_OUT : OUT std_logic
274 );
275 END COMPONENT;
276
277 component FTM_test9_rs485_interface
278 GENERIC(
279 CLOCK_FREQUENCY : integer; -- Hertz
280 BAUD_RATE : integer -- bits / sec
281 );
282 PORT(
283 clk : IN std_logic;
284 -- RS485
285 rx_d : IN std_logic;
286 rx_en : OUT std_logic;
287 tx_d : OUT std_logic;
288 tx_en : OUT std_logic;
289 -- FPGA
290 rx_data : OUT std_logic_vector(7 DOWNTO 0);
291 -- rx_busy : OUT std_logic := '0';
292 rx_valid : OUT std_logic := '0';
293 tx_data : IN std_logic_vector(7 DOWNTO 0);
294 tx_busy : OUT std_logic := '0';
295 tx_start : IN std_logic
296 );
297 end component;
298
299 signal reset_sig : STD_LOGIC := '0'; -- initialize reset to 0 at power up
300 signal clk_50M_sig : STD_LOGIC;
301
302 signal LED_red_sig : STD_LOGIC_VECTOR(3 downto 0) := (others => '1');
303 signal LED_ye_sig : STD_LOGIC_VECTOR(1 downto 0) := (others => '1');
304 signal LED_gn_sig : STD_LOGIC_VECTOR(1 downto 0) := (others => '1');
305
306 signal rx_data_sig : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
307 -- signal rx_busy_sig : STD_LOGIC;
308 signal rx_valid_sig : STD_LOGIC;
309
310 signal txcnt : integer range 0 to 28 := 0; -- count 28 1-byte frames
311
312 signal tx_start_sig : std_logic := '0';
313 signal tx_data_sig : std_logic_vector (7 DOWNTO 0) := (others => '0');
314 signal tx_busy_sig : std_logic; -- initialized in FTU_rs485_interface
315
316
317 type FTM_test9_StateType is (INIT, SEND, WAIT_FOR_ANSWER, FINISHED);
318 signal FTM_test9_State : FTM_test9_StateType;
319
320begin
321
322 Inst_FTM_test9_dcm: FTM_test9_dcm PORT MAP(
323 CLKIN_IN => clk,
324 RST_IN => reset_sig,
325 CLKFX_OUT => clk_50M_sig,
326 CLK0_OUT => open,
327 LOCKED_OUT => open
328 );
329
330 Inst_FTM_test9_rs485_interface : FTM_test9_rs485_interface
331 generic map(
332 CLOCK_FREQUENCY => 50000000,
333 BAUD_RATE => 250000
334 )
335 port map(
336 clk => clk_50M_sig,
337 -- RS485
338 rx_d => Bus1_RxD_0,
339 rx_en => Bus1_Rx_En,
340 tx_d => Bus1_TxD_0,
341 tx_en => Bus1_Tx_En,
342 -- FPGA
343 rx_data => rx_data_sig,
344 -- rx_busy => rx_busy_sig,
345 rx_valid => rx_valid_sig,
346 tx_data => tx_data_sig,
347 tx_busy => tx_busy_sig,
348 tx_start => tx_start_sig
349 );
350
351 --FTM test9 state machine
352
353 FTM_test9_FSM: process (clk_50M_sig)
354 begin
355 if Rising_edge(clk_50M_sig) then
356 case FTM_test9_State is
357
358 when INIT =>
359 LED_red_sig(0) <= '0';
360 LED_ye_sig(0) <= '1';
361 LED_gn_sig(0) <= '1';
362 FTM_test9_State <= SEND;
363
364 when SEND =>
365 LED_red_sig(0) <= '0';
366 LED_ye_sig(0) <= '1';
367 LED_gn_sig(0) <= '1';
368 if tx_busy_sig = '0' then
369 if txcnt = 0 then -- start delimiter
370 txcnt <= txcnt + 1;
371 tx_data_sig <= "01000000";
372 tx_start_sig <= '1';
373 FTM_test9_State <= SEND;
374 elsif txcnt = 1 then -- FTU address
375 txcnt <= txcnt + 1;
376 tx_data_sig <= "00111111";
377 tx_start_sig <= '1';
378 FTM_test9_State <= SEND;
379 elsif txcnt = 2 then -- FTM address
380 txcnt <= txcnt + 1;
381 tx_data_sig <= "11000000";
382 tx_start_sig <= '1';
383 FTM_test9_State <= SEND;
384 elsif txcnt = 3 then -- firmware ID
385 txcnt <= txcnt + 1;
386 tx_data_sig <= "00000001";
387 tx_start_sig <= '1';
388 FTM_test9_State <= SEND;
389 elsif txcnt = 4 then -- command
390 txcnt <= txcnt + 1;
391 tx_data_sig <= "00000000";
392 tx_start_sig <= '1';
393 FTM_test9_State <= SEND;
394 elsif txcnt = 5 then -- data: DAC A low
395 txcnt <= txcnt + 1;
396 tx_data_sig <= "00000000";
397 tx_start_sig <= '1';
398 FTM_test9_State <= SEND;
399 elsif txcnt = 6 then -- data: DAC A high
400 txcnt <= txcnt + 1;
401 tx_data_sig <= "00000000";
402 tx_start_sig <= '1';
403 FTM_test9_State <= SEND;
404 elsif txcnt = 7 then -- data: DAC B low
405 txcnt <= txcnt + 1;
406 tx_data_sig <= "00000000";
407 tx_start_sig <= '1';
408 FTM_test9_State <= SEND;
409 elsif txcnt = 8 then -- data: DAC B high
410 txcnt <= txcnt + 1;
411 tx_data_sig <= "00000000";
412 tx_start_sig <= '1';
413 FTM_test9_State <= SEND;
414 elsif txcnt = 9 then -- data: DAC C low
415 txcnt <= txcnt + 1;
416 tx_data_sig <= "00000000";
417 tx_start_sig <= '1';
418 FTM_test9_State <= SEND;
419 elsif txcnt = 10 then -- data: DAC C high
420 txcnt <= txcnt + 1;
421 tx_data_sig <= "00000000";
422 tx_start_sig <= '1';
423 FTM_test9_State <= SEND;
424 elsif txcnt = 11 then -- data: DAC D low
425 txcnt <= txcnt + 1;
426 tx_data_sig <= "00000000";
427 tx_start_sig <= '1';
428 FTM_test9_State <= SEND;
429 elsif txcnt = 12 then -- data: DAC D high
430 txcnt <= txcnt + 1;
431 tx_data_sig <= "00000000";
432 tx_start_sig <= '1';
433 FTM_test9_State <= SEND;
434 elsif txcnt = 13 then -- data: DAC E low
435 txcnt <= txcnt + 1;
436 tx_data_sig <= "00000000";
437 tx_start_sig <= '1';
438 FTM_test9_State <= SEND;
439 elsif txcnt = 14 then -- data: DAC E high
440 txcnt <= txcnt + 1;
441 tx_data_sig <= "00000000";
442 tx_start_sig <= '1';
443 FTM_test9_State <= SEND;
444 elsif txcnt < (28 - 2) then -- data: not used
445 txcnt <= txcnt + 1;
446 tx_data_sig <= "00000000";
447 tx_start_sig <= '1';
448 FTM_test9_State <= SEND;
449 elsif txcnt = (28 - 2) then -- CRC error counter
450 txcnt <= txcnt + 1;
451 tx_data_sig <= "00000000";
452 tx_start_sig <= '1';
453 FTM_test9_State <= SEND;
454 elsif txcnt = (28 - 1) then -- check sum
455 txcnt <= txcnt + 1;
456 tx_data_sig <= "00011101";
457 tx_start_sig <= '1';
458 FTM_test9_State <= SEND;
459 else -- transmission finished
460 txcnt <= 0;
461 LED_red_sig(0) <= '1';
462 LED_ye_sig(0) <= '0';
463 LED_gn_sig(0) <= '1';
464 FTM_test9_State <= WAIT_FOR_ANSWER;
465 end if;
466 else
467 tx_start_sig <= '0';
468 FTM_test9_State <= SEND;
469 end if;
470
471 when WAIT_FOR_ANSWER =>
472 LED_red_sig(0) <= '1';
473 LED_ye_sig(0) <= '0';
474 LED_gn_sig(0) <= '1';
475 if rx_valid_sig = '1' then
476 LED_red_sig(0) <= '1';
477 LED_ye_sig(0) <= '1';
478 LED_gn_sig(0) <= '0';
479 FTM_test9_State <= FINISHED;
480 else
481 FTM_test9_State <= WAIT_FOR_ANSWER;
482 end if;
483
484 when FINISHED =>
485 LED_red_sig(0) <= '1';
486 LED_ye_sig(0) <= '1';
487 LED_gn_sig(0) <= '0';
488
489 end case;
490 end if;
491 end process FTM_test9_FSM;
492
493 LED_red <= LED_red_sig;
494 LED_ye <= LED_ye_sig;
495 LED_gn <= LED_gn_sig;
496
497 LED_red_sig(3 downto 1) <= "111";
498 LED_ye_sig(1) <= '1';
499 LED_gn_sig(1) <= '1';
500
501end Behavioral;
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