source: firmware/FTM/test_firmware/FTM_test9/FTM_test9_dcm.vhd@ 10104

Last change on this file since 10104 was 10104, checked in by weitzel, 12 years ago
FTM_test9 added: check FTM-FTU communication
File size: 2.9 KB
Line 
1--------------------------------------------------------------------------------
2-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
3--------------------------------------------------------------------------------
4-- ____ ____
5-- / /\/ /
6-- /___/ \ / Vendor: Xilinx
7-- \ \ \/ Version : 11.5
8-- \ \ Application : xaw2vhdl
9-- / / Filename : FTM_test9_dcm.vhd
10-- /___/ /\ Timestamp : 01/13/2011 (copy from FTM_Test8_dcm)
11-- \ \ / \
12-- \___\/\___\
13--
14--Command: xaw2vhdl-st /ihp/home01/pavogler/Playground/FTM-Tests/FTM_Test8/FTM_Test8/ipcore_dir/FTM_Test8_dcm.xaw /ihp/home01/pavogler/Playground/FTM-Tests/FTM_Test8/FTM_Test8/ipcore_dir/FTM_Test8_dcm
15--Design Name: FTM_Test8_dcm
16--Device: xc3sd3400a-4fg676
17--
18-- Module FTM_test9_dcm
19-- Generated by Xilinx Architecture Wizard
20-- Written for synthesis tool: XST
21-- Period Jitter (unit interval) for block DCM_SP_INST = 0.04 UI
22-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.86 ns
23
24library ieee;
25use ieee.std_logic_1164.ALL;
26use ieee.numeric_std.ALL;
27library UNISIM;
28use UNISIM.Vcomponents.ALL;
29
30entity FTM_test9_dcm is
31 port ( CLKIN_IN : in std_logic;
32 RST_IN : in std_logic;
33 CLKFX_OUT : out std_logic;
34 CLK0_OUT : out std_logic;
35 LOCKED_OUT : out std_logic);
36end FTM_test9_dcm;
37
38architecture BEHAVIORAL of FTM_test9_dcm is
39 signal CLKFB_IN : std_logic;
40 signal CLKFX_BUF : std_logic;
41 signal CLK0_BUF : std_logic;
42 signal GND_BIT : std_logic;
43begin
44 GND_BIT <= '0';
45 CLK0_OUT <= CLKFB_IN;
46 CLKFX_BUFG_INST : BUFG
47 port map (I=>CLKFX_BUF,
48 O=>CLKFX_OUT);
49
50 CLK0_BUFG_INST : BUFG
51 port map (I=>CLK0_BUF,
52 O=>CLKFB_IN);
53
54 DCM_SP_INST : DCM_SP
55 generic map( CLK_FEEDBACK => "1X",
56 CLKDV_DIVIDE => 2.0,
57 CLKFX_DIVIDE => 4,
58 CLKFX_MULTIPLY => 5,
59 CLKIN_DIVIDE_BY_2 => FALSE,
60 CLKIN_PERIOD => 25.000,
61 CLKOUT_PHASE_SHIFT => "NONE",
62 DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
63 DFS_FREQUENCY_MODE => "LOW",
64 DLL_FREQUENCY_MODE => "LOW",
65 DUTY_CYCLE_CORRECTION => TRUE,
66 FACTORY_JF => x"C080",
67 PHASE_SHIFT => 0,
68 STARTUP_WAIT => FALSE)
69 port map (CLKFB=>CLKFB_IN,
70 CLKIN=>CLKIN_IN,
71 DSSEN=>GND_BIT,
72 PSCLK=>GND_BIT,
73 PSEN=>GND_BIT,
74 PSINCDEC=>GND_BIT,
75 RST=>RST_IN,
76 CLKDV=>open,
77 CLKFX=>CLKFX_BUF,
78 CLKFX180=>open,
79 CLK0=>CLK0_BUF,
80 CLK2X=>open,
81 CLK2X180=>open,
82 CLK90=>open,
83 CLK180=>open,
84 CLK270=>open,
85 LOCKED=>LOCKED_OUT,
86 PSDONE=>open,
87 STATUS=>open);
88
89end BEHAVIORAL;
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