source: firmware/FTM/test_firmware/FTM_test9/FTM_test9_tb.vhd @ 10104

Last change on this file since 10104 was 10104, checked in by weitzel, 9 years ago
FTM_test9 added: check FTM-FTU communication
File size: 4.1 KB
Line 
1--------------------------------------------------------------------------------
2-- Company:       ETH Zurich, Institute for Particle Physics
3-- Engineer:      Q. Weitzel, P. Vogler
4--
5-- Create Date:   13.01.2011
6-- Design Name:   
7-- Module Name:   FTM_test9_tb.vhd
8-- Project Name: 
9-- Target Device: 
10-- Tool versions: 
11-- Description:   Testbench for FTM - FTU RS485 test
12--
13-- VHDL Test Bench Created by ISE for module: FTM_test9
14--
15-- Dependencies:
16--
17-- Revision:
18-- Revision 0.01 - File Created
19-- Additional Comments:
20--
21-- Notes:
22-- This testbench has been automatically generated using types std_logic and
23-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
24-- that these types always be used for the top-level I/O of a design in order
25-- to guarantee that the testbench will bind correctly to the post-implementation
26-- simulation model.
27--------------------------------------------------------------------------------
28library IEEE;
29use IEEE.STD_LOGIC_1164.ALL;
30use IEEE.STD_LOGIC_UNSIGNED.ALL;
31use IEEE.NUMERIC_STD.ALL;
32
33library UNISIM;
34use UNISIM.VComponents.all;
35
36entity FTU_test9_tb is
37end FTU_test9_tb;
38
39architecture behavior of FTU_test9_tb is 
40
41  -- Component Declaration for the Unit Under Test (UUT)
42 
43  component FTM_test9
44    port(
45      clk        : in  STD_LOGIC;
46      LED_red    : out STD_LOGIC_VECTOR(3 downto 0);
47      LED_ye     : out STD_LOGIC_VECTOR(1 downto 0);
48      LED_gn     : out STD_LOGIC_VECTOR(1 downto 0);
49      Bus1_Tx_En : out STD_LOGIC;
50      Bus1_Rx_En : out STD_LOGIC;
51      Bus1_RxD_0 : in STD_LOGIC;
52      Bus1_TxD_0 : out STD_LOGIC
53    );
54  end component;
55   
56  --Inputs
57  signal clk_sig        : STD_LOGIC := '0';
58  signal Bus1_RxD_0_sig : STD_LOGIC := '1';
59
60  --Outputs
61  signal LED_red_sig    : STD_LOGIC_VECTOR(3 downto 0);
62  signal LED_ye_sig     : STD_LOGIC_VECTOR(1 downto 0);
63  signal LED_gn_sig     : STD_LOGIC_VECTOR(1 downto 0);
64  signal Bus1_Tx_En_sig : STD_LOGIC;
65  signal Bus1_Rx_En_sig : STD_LOGIC;
66  signal Bus1_TxD_0_sig : STD_LOGIC;
67 
68  -- Clock period definitions
69  constant clk_period : TIME := 25 ns;
70  constant baud_rate_period : TIME := 4 us;
71 
72begin
73 
74  -- Instantiate the Unit Under Test (UUT)
75  uut: FTM_test9
76    port map(
77      clk        => clk_sig,
78      LED_red    => LED_red_sig,
79      LED_ye     => LED_ye_sig,
80      LED_gn     => LED_gn_sig,
81      Bus1_Tx_En => Bus1_Tx_En_sig,
82      Bus1_Rx_En => Bus1_Rx_En_sig,
83      Bus1_RxD_0 => Bus1_RxD_0_sig,
84      Bus1_TxD_0 => Bus1_TxD_0_sig
85    );
86
87  -- Stimulus process for clock
88  clk_proc: process
89  begin
90    clk_sig <= '0';
91    wait for clk_period/2;
92    clk_sig <= '1';
93    wait for clk_period/2;
94  end process clk_proc;
95 
96  -- Stimulus process for RS485
97  rs485_proc: process
98   
99    procedure assign_rs485 (data: std_logic_vector(7 downto 0)) is
100    begin
101      Bus1_RxD_0_sig <= '0'; --start bit
102      wait for baud_rate_period;
103      Bus1_RxD_0_sig <= data(0); --bit 0
104      wait for baud_rate_period;
105      Bus1_RxD_0_sig <= data(1); --bit 1
106      wait for baud_rate_period;
107      Bus1_RxD_0_sig <= data(2); --bit 2
108      wait for baud_rate_period;
109      Bus1_RxD_0_sig <= data(3); --bit 3
110      wait for baud_rate_period;
111      Bus1_RxD_0_sig <= data(4); --bit 4
112      wait for baud_rate_period;
113      Bus1_RxD_0_sig <= data(5); --bit 5
114      wait for baud_rate_period;
115      Bus1_RxD_0_sig <= data(6); --bit 6
116      wait for baud_rate_period;
117      Bus1_RxD_0_sig <= data(7); --bit 7
118      wait for baud_rate_period;
119      Bus1_RxD_0_sig <= '1'; --stop bit
120      wait for baud_rate_period;
121      Bus1_RxD_0_sig <= '1'; --stop bit
122      wait for baud_rate_period;
123    end assign_rs485;
124   
125  begin
126    wait for 1500us;
127    ---------------------------------------------------------------------------
128    -- send a '@' character
129    ---------------------------------------------------------------------------
130    assign_rs485("01000000");
131    ---------------------------------------------------------------------------
132    -- don't forget final wait!
133    ---------------------------------------------------------------------------
134    wait;
135   
136  end process rs485_proc;
137
138end;
Note: See TracBrowser for help on using the repository browser.