--
-- VHDL Architecture FACT_FTM_Boards.counter_dummy.beha
--
-- Created:
--          by - kai.users (tpkw.local.priv)
--          at - 15:37:00 04/13/11
--
-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

ENTITY counter_dummy IS
   PORT( 
      clk                 : IN     std_logic;
      get_counter         : IN     std_logic;
      get_counter_started : OUT    std_logic                      := '0';
      get_counter_ready   : OUT    std_logic                      := '0';
      counter             : OUT    std_logic_vector (47 DOWNTO 0) := (others => '0')
   );

-- Declarations

END counter_dummy ;

--
ARCHITECTURE beha OF counter_dummy IS
  
  type state_counter_proc_type is (CP_INIT, CP_CONFIG, CP_IDLE, CP_CNT_START, CP_CNT_END);
  signal state_counter_proc : state_counter_proc_type := CP_INIT;
  
  signal counter_int : std_logic_vector (47 DOWNTO 0) := (others => '0');
  
BEGIN
  counter_proc : process (clk)
  begin
    if rising_edge (clk) then
      case state_counter_proc is
        
        when CP_INIT =>
          state_counter_proc <= CP_CONFIG;
          
        when CP_CONFIG =>
          state_counter_proc <= CP_IDLE;
          
        when CP_IDLE =>
          if (get_counter = '1') then
            counter_int <= counter_int + 1;
            get_counter_started <= '1';
            get_counter_ready <= '0';
            state_counter_proc <= CP_CNT_START;
          end if;
          
        when CP_CNT_START =>
          counter <= counter_int;
          state_counter_proc <= CP_CNT_END;
          
        when CP_CNT_END =>
          if (get_counter = '0') then
            get_counter_started <= '0';
            get_counter_ready <= '1';
            state_counter_proc <= CP_IDLE;
          end if;
          
      end case;    
    end if;
  end process counter_proc;

END ARCHITECTURE beha;