source: firmware/FTM/trigger/assembler/FTU_trigger_generator/FTU_trigger_counter.vhd@ 16369

Last change on this file since 16369 was 10366, checked in by weitzel, 15 years ago
FTM trigger manager from MCSE added; DCM arrangement changed; changes in FTM ethernet module
File size: 8.4 KB
Line 
1--=======================================================================================
2-- TITLE : Trigger counter top
3-- DESCRIPTION : Top entity for trigger synchronization, detection and counting
4-- FILE : FTU_trigger_counter.vhd
5-- COMPANY : Micro-Cameras & Space Exploration SA
6--=======================================================================================
7-- CREATION
8-- DATE AUTHOR PROJECT REVISION
9-- 02/03/2011 JGi FTM 110302a
10--=======================================================================================
11-- MODIFICATION HISTORY
12-- DATE AUTHOR PROJECT REVISION COMMENTS
13-- 02/03/2011 JGi FTM 110302a Description
14--=======================================================================================
15-- Library Definition
16library ieee;
17 use ieee.std_logic_1164.all;
18 use ieee.numeric_std.all;
19
20-- Entity Definition
21entity FTU_trigger_counter is
22 port( --clocks
23 clk_250MHz : in std_logic;
24 clk_250MHz_180 : in std_logic;
25 --control
26 phys_coinc_window : in std_logic_vector(3 downto 0);
27 calib_coinc_window : in std_logic_vector(3 downto 0);
28 active_FTU_list_0 : in std_logic_vector(9 downto 0);
29 active_FTU_list_1 : in std_logic_vector(9 downto 0);
30 active_FTU_list_2 : in std_logic_vector(9 downto 0);
31 active_FTU_list_3 : in std_logic_vector(9 downto 0);
32 --trigger primitives from FTUs
33 trig_prim_0 : in std_logic_vector(9 downto 0); --crate 0
34 trig_prim_1 : in std_logic_vector(9 downto 0); --crate 1
35 trig_prim_2 : in std_logic_vector(9 downto 0); --crate 2
36 trig_prim_3 : in std_logic_vector(9 downto 0); --crate 3
37 --trigger detection pulses
38 phys_events : out std_logic_vector(5 downto 0);
39 calib_events : out std_logic_vector(5 downto 0));
40end FTU_trigger_counter;
41
42-- Architecture Definition
43architecture RTL of FTU_trigger_counter is
44
45 component input_synch is
46 port( clk_250MHz : in std_logic;
47 clk_250MHz_180 : in std_logic;
48 trig_prim_0 : in std_logic_vector(9 downto 0);
49 trig_prim_1 : in std_logic_vector(9 downto 0);
50 trig_prim_2 : in std_logic_vector(9 downto 0);
51 trig_prim_3 : in std_logic_vector(9 downto 0);
52 trig_synch_0_rise : out std_logic_vector(9 downto 0);
53 trig_synch_1_rise : out std_logic_vector(9 downto 0);
54 trig_synch_2_rise : out std_logic_vector(9 downto 0);
55 trig_synch_3_rise : out std_logic_vector(9 downto 0);
56 trig_synch_0_fall : out std_logic_vector(9 downto 0);
57 trig_synch_1_fall : out std_logic_vector(9 downto 0);
58 trig_synch_2_fall : out std_logic_vector(9 downto 0);
59 trig_synch_3_fall : out std_logic_vector(9 downto 0));
60 end component;
61
62 signal i_trig_synch_0_rise : std_logic_vector(9 downto 0);
63 signal i_trig_synch_1_rise : std_logic_vector(9 downto 0);
64 signal i_trig_synch_2_rise : std_logic_vector(9 downto 0);
65 signal i_trig_synch_3_rise : std_logic_vector(9 downto 0);
66 signal i_trig_synch_0_fall : std_logic_vector(9 downto 0);
67 signal i_trig_synch_1_fall : std_logic_vector(9 downto 0);
68 signal i_trig_synch_2_fall : std_logic_vector(9 downto 0);
69 signal i_trig_synch_3_fall : std_logic_vector(9 downto 0);
70
71 component time_window is
72 port( clk_250MHz : in std_logic;
73 coinc_window : in std_logic_vector(3 downto 0);
74 active_FTU_list_0 : in std_logic_vector(9 downto 0);
75 active_FTU_list_1 : in std_logic_vector(9 downto 0);
76 active_FTU_list_2 : in std_logic_vector(9 downto 0);
77 active_FTU_list_3 : in std_logic_vector(9 downto 0);
78 trig_synch_0_rise : in std_logic_vector(9 downto 0);
79 trig_synch_1_rise : in std_logic_vector(9 downto 0);
80 trig_synch_2_rise : in std_logic_vector(9 downto 0);
81 trig_synch_3_rise : in std_logic_vector(9 downto 0);
82 trig_synch_0_fall : in std_logic_vector(9 downto 0);
83 trig_synch_1_fall : in std_logic_vector(9 downto 0);
84 trig_synch_2_fall : in std_logic_vector(9 downto 0);
85 trig_synch_3_fall : in std_logic_vector(9 downto 0);
86 trig_window_0 : out std_logic_vector(9 downto 0);
87 trig_window_1 : out std_logic_vector(9 downto 0);
88 trig_window_2 : out std_logic_vector(9 downto 0);
89 trig_window_3 : out std_logic_vector(9 downto 0));
90 end component;
91
92 signal i_trig_phys_window_0 : std_logic_vector(9 downto 0);
93 signal i_trig_phys_window_1 : std_logic_vector(9 downto 0);
94 signal i_trig_phys_window_2 : std_logic_vector(9 downto 0);
95 signal i_trig_phys_window_3 : std_logic_vector(9 downto 0);
96 signal i_trig_calib_window_0 : std_logic_vector(9 downto 0);
97 signal i_trig_calib_window_1 : std_logic_vector(9 downto 0);
98 signal i_trig_calib_window_2 : std_logic_vector(9 downto 0);
99 signal i_trig_calib_window_3 : std_logic_vector(9 downto 0);
100
101 component trigger_sum is
102 port( clk_250MHz : in std_logic;
103 trig_window_0 : in std_logic_vector(9 downto 0);
104 trig_window_1 : in std_logic_vector(9 downto 0);
105 trig_window_2 : in std_logic_vector(9 downto 0);
106 trig_window_3 : in std_logic_vector(9 downto 0);
107 number_of_events : out std_logic_vector(5 downto 0));
108 end component;
109
110begin
111
112 -- Component instantiation
113 inst_synch: input_synch
114 port map( clk_250MHz => clk_250MHz,
115 clk_250MHz_180 => clk_250MHz_180,
116 trig_prim_0 => trig_prim_0,
117 trig_prim_1 => trig_prim_1,
118 trig_prim_2 => trig_prim_2,
119 trig_prim_3 => trig_prim_3,
120 trig_synch_0_rise => i_trig_synch_0_rise,
121 trig_synch_1_rise => i_trig_synch_1_rise,
122 trig_synch_2_rise => i_trig_synch_2_rise,
123 trig_synch_3_rise => i_trig_synch_3_rise,
124 trig_synch_0_fall => i_trig_synch_0_fall,
125 trig_synch_1_fall => i_trig_synch_1_fall,
126 trig_synch_2_fall => i_trig_synch_2_fall,
127 trig_synch_3_fall => i_trig_synch_3_fall);
128
129 inst_phys_window: time_window
130 port map( clk_250MHz => clk_250MHz,
131 coinc_window => phys_coinc_window,
132 active_FTU_list_0 => active_FTU_list_0,
133 active_FTU_list_1 => active_FTU_list_1,
134 active_FTU_list_2 => active_FTU_list_2,
135 active_FTU_list_3 => active_FTU_list_3,
136 trig_synch_0_rise => i_trig_synch_0_rise,
137 trig_synch_1_rise => i_trig_synch_1_rise,
138 trig_synch_2_rise => i_trig_synch_2_rise,
139 trig_synch_3_rise => i_trig_synch_3_rise,
140 trig_synch_0_fall => i_trig_synch_0_fall,
141 trig_synch_1_fall => i_trig_synch_1_fall,
142 trig_synch_2_fall => i_trig_synch_2_fall,
143 trig_synch_3_fall => i_trig_synch_3_fall,
144 trig_window_0 => i_trig_phys_window_0,
145 trig_window_1 => i_trig_phys_window_1,
146 trig_window_2 => i_trig_phys_window_2,
147 trig_window_3 => i_trig_phys_window_3);
148
149 inst_calib_window: time_window
150 port map( clk_250MHz => clk_250MHz,
151 coinc_window => calib_coinc_window,
152 active_FTU_list_0 => active_FTU_list_0,
153 active_FTU_list_1 => active_FTU_list_1,
154 active_FTU_list_2 => active_FTU_list_2,
155 active_FTU_list_3 => active_FTU_list_3,
156 trig_synch_0_rise => i_trig_synch_0_rise,
157 trig_synch_1_rise => i_trig_synch_1_rise,
158 trig_synch_2_rise => i_trig_synch_2_rise,
159 trig_synch_3_rise => i_trig_synch_3_rise,
160 trig_synch_0_fall => i_trig_synch_0_fall,
161 trig_synch_1_fall => i_trig_synch_1_fall,
162 trig_synch_2_fall => i_trig_synch_2_fall,
163 trig_synch_3_fall => i_trig_synch_3_fall,
164 trig_window_0 => i_trig_calib_window_0,
165 trig_window_1 => i_trig_calib_window_1,
166 trig_window_2 => i_trig_calib_window_2,
167 trig_window_3 => i_trig_calib_window_3);
168
169 inst_phys_final_sum: trigger_sum
170 port map( clk_250MHz => clk_250MHz,
171 trig_window_0 => i_trig_phys_window_0,
172 trig_window_1 => i_trig_phys_window_1,
173 trig_window_2 => i_trig_phys_window_2,
174 trig_window_3 => i_trig_phys_window_3,
175 number_of_events => phys_events);
176
177 inst_calib_final_sum: trigger_sum
178 port map( clk_250MHz => clk_250MHz,
179 trig_window_0 => i_trig_calib_window_0,
180 trig_window_1 => i_trig_calib_window_1,
181 trig_window_2 => i_trig_calib_window_2,
182 trig_window_3 => i_trig_calib_window_3,
183 number_of_events => calib_events);
184
185end RTL;
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