source: firmware/FTM/trigger/drivers/calibration_pedestal/calibration_pedestal.vhd@ 16369

Last change on this file since 16369 was 10366, checked in by weitzel, 15 years ago
FTM trigger manager from MCSE added; DCM arrangement changed; changes in FTM ethernet module
File size: 10.5 KB
Line 
1--=======================================================================================
2-- TITLE : Calibration and pedestal triggers generation
3-- DESCRIPTION : Generate LP1, LP2 and PEDESTAL pulses for calibration runs
4-- FILE : calibration_pedestal.vhd
5-- COMPANY : Micro-Cameras & Space Exploration SA
6--=======================================================================================
7-- CREATION
8-- DATE AUTHOR PROJECT REVISION
9-- 11/03/2011 JGi 110311a
10--=======================================================================================
11-- MODIFICATION HISTORY
12-- DATE AUTHOR PROJECT REVISION COMMENTS
13-- 11/03/2011 JGi 110311a Description
14-- 13/04/2011 JGi 110413a Update pulse enable management to allow the
15-- same pulse to be enabled if no others are.
16--=======================================================================================
17-- Library Definition
18library ieee;
19 use ieee.std_logic_1164.all;
20 use ieee.numeric_std.all;
21
22library ftm_definitions;
23 use ftm_definitions.ftm_array_types.all;
24 use ftm_definitions.ftm_constants.all;
25
26-- Entity Definition
27entity calibration_pedestal is
28 port( --clock
29 clk_50MHz : in std_logic;
30 --control
31 new_config : in std_logic;
32 --settings
33 general_settings : in std_logic_vector(7 downto 0);
34 LP_and_PED_freq : in std_logic_vector(9 downto 0);
35 LP1_LP2_PED_ratio : in std_logic_vector(14 downto 0);
36 --outputs
37 LP1_pulse : out std_logic; --send start signal to light pulser 1
38 LP2_pulse : out std_logic; --send start signal to light pulser 2
39 PED_pulse : out std_logic);
40end calibration_pedestal;
41
42-- Architecture Definition
43architecture RTL of calibration_pedestal is
44
45 type t_reg is record
46 -- Internal register declaration
47 new_config : std_logic;
48 general_settings : std_logic_vector(7 downto 0);
49 LP_and_PED_freq : std_logic_vector(9 downto 0);
50 LP1_LP2_PED_ratio : std_logic_vector(14 downto 0);
51 ms_counter : unsigned(MAX_MS_COUNTER_WIDTH-1 downto 0);
52 ms_tick : std_logic;
53 tick_counter : unsigned(9 downto 0);
54 trigger_tick : std_logic;
55 trigger_counter : unsigned(4 downto 0);
56 enable_LP1 : std_logic;
57 enable_LP2 : std_logic;
58 enable_PED : std_logic;
59 -- Ouput register declaration
60 LP1_pulse : std_logic;
61 LP2_pulse : std_logic;
62 PED_pulse : std_logic;
63 end record;
64
65 signal i_next_reg : t_reg := (new_config => '0',
66 general_settings => (others => '0'),
67 LP_and_PED_freq => (others => '0'),
68 LP1_LP2_PED_ratio => (others => '0'),
69 ms_counter => (others => '0'),
70 ms_tick => '0',
71 tick_counter => (others => '0'),
72 trigger_tick => '0',
73 trigger_counter => (others => '0'),
74 enable_LP1 => '0',
75 enable_LP2 => '0',
76 enable_PED => '0',
77 LP1_pulse => '0',
78 LP2_pulse => '0',
79 PED_pulse => '0');
80 signal i_reg : t_reg := (new_config => '0',
81 general_settings => (others => '0'),
82 LP_and_PED_freq => (others => '0'),
83 LP1_LP2_PED_ratio => (others => '0'),
84 ms_counter => (others => '0'),
85 ms_tick => '0',
86 tick_counter => (others => '0'),
87 trigger_tick => '0',
88 trigger_counter => (others => '0'),
89 enable_LP1 => '0',
90 enable_LP2 => '0',
91 enable_PED => '0',
92 LP1_pulse => '0',
93 LP2_pulse => '0',
94 PED_pulse => '0');
95
96begin
97
98 -- Combinatorial logic
99 process(new_config, general_settings, LP_and_PED_freq,
100 LP1_LP2_PED_ratio, i_reg)
101 variable v_reg : t_reg := (new_config => '0',
102 general_settings => (others => '0'),
103 LP_and_PED_freq => (others => '0'),
104 LP1_LP2_PED_ratio => (others => '0'),
105 ms_counter => (others => '0'),
106 ms_tick => '0',
107 tick_counter => (others => '0'),
108 trigger_tick => '0',
109 trigger_counter => (others => '0'),
110 enable_LP1 => '0',
111 enable_LP2 => '0',
112 enable_PED => '0',
113 LP1_pulse => '0',
114 LP2_pulse => '0',
115 PED_pulse => '0');
116 begin
117 v_reg := i_reg;
118 --===================================================================================
119
120 --===================================================================================
121 -- Milliseconds counter
122 --===================================================================================
123 v_reg.ms_tick := '0';
124
125 -- Counter management
126 -- Count until 1ms is reached
127 if i_reg.ms_counter = to_unsigned(MAX_MS_COUNTER_VAL, MAX_MS_COUNTER_WIDTH)-1 then
128 v_reg.ms_counter := (others => '0');
129 v_reg.ms_tick := '1';
130 else
131 v_reg.ms_counter := i_reg.ms_counter+1;
132 end if;
133 --===================================================================================
134
135 --===================================================================================
136 -- Triggers counter
137 --===================================================================================
138 v_reg.trigger_tick := '0';
139
140 -- Generate a tick each time the pulse generation period is reached
141 if i_reg.tick_counter = unsigned(i_reg.LP_and_PED_freq(9 downto 0)) then
142 v_reg.tick_counter := (others => '0');
143 v_reg.trigger_tick := '1';
144 elsif i_reg.ms_tick = '1' then
145 v_reg.tick_counter := i_reg.tick_counter+1;
146 end if;
147 --===================================================================================
148
149 --===================================================================================
150 -- Triggers management
151 --===================================================================================
152 v_reg.new_config := new_config;
153
154 -- Register parameters when new configuration is set
155 if new_config = '1' and i_reg.new_config = '0' then
156 v_reg.general_settings := general_settings;
157 v_reg.LP_and_PED_freq := LP_and_PED_freq;
158 v_reg.LP1_LP2_PED_ratio := LP1_LP2_PED_ratio;
159 end if;
160
161 -- Manages pulses
162 if i_reg.enable_LP1 = '1' then
163 -- Wait for set number of pulse of LP1
164 if i_reg.trigger_tick = '1' then
165 v_reg.trigger_counter := i_reg.trigger_counter+1;
166 -- If number of pulse reached
167 elsif i_reg.trigger_counter = unsigned(i_reg.LP1_LP2_PED_ratio(4 downto 0)) then
168 v_reg.trigger_counter := (others => '0');
169 v_reg.enable_LP1 := '0';
170 -- Switch to next pulse enable
171 if i_reg.general_settings(5) = '1' then
172 v_reg.enable_LP2 := '1';
173 elsif i_reg.general_settings(6) = '1' then
174 v_reg.enable_PED := '1';
175 elsif i_reg.general_settings(4) = '1' then
176 v_reg.enable_LP1 := '1';
177 end if;
178 end if;
179 elsif i_reg.enable_LP2 = '1' then
180 -- Wait for set number of pulse of LP2
181 if i_reg.trigger_tick = '1' then
182 v_reg.trigger_counter := i_reg.trigger_counter+1;
183 -- If number of pulse reached
184 elsif i_reg.trigger_counter = unsigned(i_reg.LP1_LP2_PED_ratio(9 downto 5)) then
185 v_reg.trigger_counter := (others => '0');
186 v_reg.enable_LP2 := '0';
187 -- Switch to next pulse enable
188 if i_reg.general_settings(6) = '1' then
189 v_reg.enable_PED := '1';
190 elsif i_reg.general_settings(4) = '1' then
191 v_reg.enable_LP1 := '1';
192 elsif i_reg.general_settings(5) = '1' then
193 v_reg.enable_LP2 := '1';
194 end if;
195 end if;
196 elsif i_reg.enable_PED = '1' then
197 -- Wait for set number of pulse of PED
198 if i_reg.trigger_tick = '1' then
199 v_reg.trigger_counter := i_reg.trigger_counter+1;
200 -- If number of pulse reached
201 elsif i_reg.trigger_counter = unsigned(i_reg.LP1_LP2_PED_ratio(14 downto 10)) then
202 v_reg.trigger_counter := (others => '0');
203 v_reg.enable_PED := '0';
204 -- Switch to next pulse enable
205 if i_reg.general_settings(4) = '1' then
206 v_reg.enable_LP1 := '1';
207 elsif i_reg.general_settings(5) = '1' then
208 v_reg.enable_LP2 := '1';
209 elsif i_reg.general_settings(6) = '1' then
210 v_reg.enable_PED := '1';
211 end if;
212 end if;
213 else
214 v_reg.trigger_counter := (others => '0');
215 end if;
216
217 -- Enable first selected pulse when new configuration is registered
218 -- It's made after ratio counter to avoid error if new configuration
219 -- is done on the same time pulse enables change in the ratio counter
220 if new_config = '0' and i_reg.new_config = '1' then
221 v_reg.enable_LP1 := '0';
222 v_reg.enable_LP2 := '0';
223 v_reg.enable_PED := '0';
224 if i_reg.general_settings(4) = '1' then
225 v_reg.enable_LP1 := '1';
226 elsif i_reg.general_settings(5) = '1' then
227 v_reg.enable_LP2 := '1';
228 elsif i_reg.general_settings(6) = '1' then
229 v_reg.enable_PED := '1';
230 end if;
231 end if;
232
233 -- Set enabled pulse on output
234 if i_reg.trigger_tick = '1' then
235 if i_reg.enable_LP1 = '1' then
236 v_reg.LP1_pulse := '1';
237 elsif i_reg.enable_LP2 = '1' then
238 v_reg.LP2_pulse := '1';
239 elsif i_reg.enable_PED = '1' then
240 v_reg.PED_pulse := '1';
241 end if;
242 -- Once set, pulse is reset
243 else
244 v_reg.LP1_pulse := '0';
245 v_reg.LP2_pulse := '0';
246 v_reg.PED_pulse := '0';
247 end if;
248 --===================================================================================
249
250 --===================================================================================
251 -- Drive register input
252 i_next_reg <= v_reg;
253
254 --===================================================================================
255 -- Output assignation
256 LP1_pulse <= i_reg.LP1_pulse;
257 LP2_pulse <= i_reg.LP2_pulse;
258 PED_pulse <= i_reg.PED_pulse;
259 --===================================================================================
260 end process;
261
262 -- Sequential logic
263 process(clk_50MHz)
264 begin
265 if rising_edge(clk_50MHz) then
266 i_reg <= i_next_reg;
267 end if;
268 end process;
269
270end RTL;
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