source: firmware/FTM/trigger/drivers/deadtime_generator/deadtime_generator.vhd@ 17841

Last change on this file since 17841 was 10366, checked in by weitzel, 15 years ago
FTM trigger manager from MCSE added; DCM arrangement changed; changes in FTM ethernet module
File size: 6.5 KB
Line 
1--=======================================================================================
2-- TITLE : Deadtime manager
3-- DESCRIPTION : Timer for deadtime generation
4-- FILE : deadtime_generator.vhd
5-- COMPANY : Micro-Cameras & Space Exploration SA
6--=======================================================================================
7-- CREATION
8-- DATE AUTHOR PROJECT REVISION
9-- 02/03/2011 JGi FTM 110302a
10--=======================================================================================
11-- MODIFICATION HISTORY
12-- DATE AUTHOR PROJECT REVISION COMMENTS
13-- 02/03/2011 JGi FTM 110302a Description
14-- 13/04/2011 JGi FTM 110413a Remove unused signal
15--=======================================================================================
16-- Library Definition
17library ieee;
18 use ieee.std_logic_1164.all;
19 use ieee.numeric_std.all;
20
21-- Entity Definition
22entity deadtime_generator is
23 port( --clock
24 clk_250MHz : in std_logic;
25 --control
26 deadtime : in std_logic_vector(15 downto 0);
27 --I/O
28 start : in std_logic;
29 waiting : out std_logic);
30end deadtime_generator;
31
32-- Architecture Definition
33architecture RTL of deadtime_generator is
34
35 type t_reg is record
36 -- Internal register declaration
37 deadtime : std_logic_vector(15 downto 0);
38 deadtime_counter : std_logic_vector(15 downto 0);
39 deadtime_value_reached : std_logic_vector(3 downto 0);
40 deadtime_0_done : std_logic_vector(2 downto 0);
41 deadtime_1_done : std_logic_vector(1 downto 0);
42 deadtime_2_done : std_logic;
43 -- Ouput register declaration
44 busy : std_logic_vector(2 downto 0);
45 end record;
46
47 signal i_next_reg : t_reg := (deadtime => (others => '0'),
48 deadtime_counter => (others => '0'),
49 deadtime_value_reached => (others => '0'),
50 deadtime_0_done => (others => '0'),
51 deadtime_1_done => (others => '0'),
52 deadtime_2_done => '0',
53 busy => (others => '0'));
54 signal i_reg : t_reg := (deadtime => (others => '0'),
55 deadtime_counter => (others => '0'),
56 deadtime_value_reached => (others => '0'),
57 deadtime_0_done => (others => '0'),
58 deadtime_1_done => (others => '0'),
59 deadtime_2_done => '0',
60 busy => (others => '0'));
61
62begin
63
64 -- Combinatorial logic
65 process(start, deadtime, i_reg)
66 variable v_reg : t_reg := (deadtime => (others => '0'),
67 deadtime_counter => (others => '0'),
68 deadtime_value_reached => (others => '0'),
69 deadtime_0_done => (others => '0'),
70 deadtime_1_done => (others => '0'),
71 deadtime_2_done => '0',
72 busy => (others => '0'));
73 begin
74 v_reg := i_reg;
75 --===================================================================================
76
77 --===================================================================================
78 -- Counter management
79 --===================================================================================
80 -- Register deadtime to reduce delay
81 v_reg.deadtime := deadtime;
82
83 -- If deadtime enabled, count
84 if i_reg.busy(0) = '1' then
85 v_reg.deadtime_counter(3 downto 0) :=
86 std_logic_vector(unsigned(i_reg.deadtime_counter(3 downto 0))+1);
87 if i_reg.deadtime_0_done(2) = '1' then
88 v_reg.deadtime_counter(7 downto 4) :=
89 std_logic_vector(unsigned(i_reg.deadtime_counter(7 downto 4))+1);
90 end if;
91 if i_reg.deadtime_1_done(1) = '1' then
92 v_reg.deadtime_counter(11 downto 8) :=
93 std_logic_vector(unsigned(i_reg.deadtime_counter(11 downto 8))+1);
94 end if;
95 if i_reg.deadtime_2_done = '1' then
96 v_reg.deadtime_counter(15 downto 12) :=
97 std_logic_vector(unsigned(i_reg.deadtime_counter(15 downto 12))+1);
98 end if;
99 else
100 v_reg.deadtime_counter := (others => '0');
101 end if;
102
103 -- If counter reached the deadtime value
104 if i_reg.deadtime_value_reached = "1111" then
105 v_reg.busy := (others => '0');
106 end if;
107
108 -- Start when input goes high
109 if start = '1' then
110 v_reg.busy := (others => '1');
111 end if;
112
113 -- Generate partial comparison to the programmed deadtime value
114 if i_reg.deadtime_counter(3 downto 0) = i_reg.deadtime(3 downto 0) then
115 v_reg.deadtime_value_reached(0) := i_reg.busy(1);
116 else
117 v_reg.deadtime_value_reached(0) := '0';
118 end if;
119 if i_reg.deadtime_counter(7 downto 4) = i_reg.deadtime(7 downto 4) then
120 v_reg.deadtime_value_reached(1) := i_reg.busy(1);
121 else
122 v_reg.deadtime_value_reached(1) := '0';
123 end if;
124 if i_reg.deadtime_counter(11 downto 8) = i_reg.deadtime(11 downto 8) then
125 v_reg.deadtime_value_reached(2) := i_reg.busy(1);
126 else
127 v_reg.deadtime_value_reached(2) := '0';
128 end if;
129 if i_reg.deadtime_counter(15 downto 12) = i_reg.deadtime(15 downto 12) then
130 v_reg.deadtime_value_reached(3) := i_reg.busy(1);
131 else
132 v_reg.deadtime_value_reached(3) := '0';
133 end if;
134
135 -- Manage partial counters enable
136 if i_reg.deadtime_counter(3 downto 0) = "1100" then
137 v_reg.deadtime_0_done(0) := '1';
138 else
139 v_reg.deadtime_0_done(0) := '0';
140 end if;
141 v_reg.deadtime_0_done(1) := i_reg.deadtime_0_done(0);
142 v_reg.deadtime_0_done(2) := i_reg.deadtime_0_done(1);
143
144 if i_reg.deadtime_counter(7 downto 4) = "1111" then
145 v_reg.deadtime_1_done(0) := i_reg.deadtime_0_done(0);
146 else
147 v_reg.deadtime_1_done(0) := '0';
148 end if;
149 v_reg.deadtime_1_done(1) := i_reg.deadtime_1_done(0);
150
151 if i_reg.deadtime_counter(11 downto 8) = "1111" then
152 v_reg.deadtime_2_done := i_reg.deadtime_0_done(1) and i_reg.deadtime_1_done(0);
153 else
154 v_reg.deadtime_2_done := '0';
155 end if;
156 --===================================================================================
157
158 --===================================================================================
159 -- Drive register input
160 i_next_reg <= v_reg;
161
162 --===================================================================================
163 -- Output assignation
164 waiting <= i_reg.busy(2);
165 --===================================================================================
166 end process;
167
168 -- Sequential logic
169 process(clk_250MHz)
170 begin
171 if rising_edge(clk_250MHz) then
172 i_reg <= i_next_reg;
173 end if;
174 end process;
175
176end RTL;
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