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-- You must compile the wrapper file adder_3_bits.vhd when simulating
-- the core, adder_3_bits. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY adder_3_bits IS
	port (
	a: IN std_logic_VECTOR(2 downto 0);
	b: IN std_logic_VECTOR(2 downto 0);
	clk: IN std_logic;
	s: OUT std_logic_VECTOR(3 downto 0));
END adder_3_bits;

ARCHITECTURE adder_3_bits_a OF adder_3_bits IS
-- synthesis translate_off
component wrapped_adder_3_bits
	port (
	a: IN std_logic_VECTOR(2 downto 0);
	b: IN std_logic_VECTOR(2 downto 0);
	clk: IN std_logic;
	s: OUT std_logic_VECTOR(3 downto 0));
end component;

-- Configuration specification 
	for all : wrapped_adder_3_bits use entity XilinxCoreLib.c_addsub_v11_0(behavioral)
		generic map(
			c_a_width => 3,
			c_out_width => 4,
			c_add_mode => 0,
			c_has_c_out => 0,
			c_b_type => 1,
			c_borrow_low => 1,
			c_ce_overrides_sclr => 0,
			c_implementation => 0,
			c_has_sclr => 0,
			c_verbosity => 0,
			c_latency => 1,
			c_has_bypass => 0,
			c_ainit_val => "0",
			c_bypass_low => 0,
			c_has_ce => 0,
			c_sclr_overrides_sset => 0,
			c_sinit_val => "0",
			c_has_sset => 0,
			c_has_c_in => 0,
			c_has_sinit => 0,
			c_b_constant => 0,
			c_ce_overrides_bypass => 1,
			c_xdevicefamily => "spartan3adsp",
			c_a_type => 1,
			c_b_width => 3,
			c_b_value => "000");
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_adder_3_bits
		port map (
			a => a,
			b => b,
			clk => clk,
			s => s);
-- synthesis translate_on

END adder_3_bits_a;