| 1 | --------------------------------------------------------------------------------
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| 2 | -- This file is owned and controlled by Xilinx and must be used --
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| 3 | -- solely for design, simulation, implementation and creation of --
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| 4 | -- design files limited to Xilinx devices or technologies. Use --
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| 5 | -- with non-Xilinx devices or technologies is expressly prohibited --
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| 6 | -- and immediately terminates your license. --
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| 7 | -- --
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| 8 | -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
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| 9 | -- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
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| 10 | -- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
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| 11 | -- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
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| 12 | -- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
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| 13 | -- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
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| 14 | -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
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| 15 | -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
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| 16 | -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
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| 17 | -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
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| 18 | -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
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| 19 | -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
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| 20 | -- FOR A PARTICULAR PURPOSE. --
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| 21 | -- --
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| 22 | -- Xilinx products are not intended for use in life support --
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| 23 | -- appliances, devices, or systems. Use in such applications are --
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| 24 | -- expressly prohibited. --
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| 25 | -- --
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| 26 | -- (c) Copyright 1995-2009 Xilinx, Inc. --
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| 27 | -- All rights reserved. --
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| 28 | --------------------------------------------------------------------------------
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| 29 | -- You must compile the wrapper file adder_5_bits.vhd when simulating
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| 30 | -- the core, adder_5_bits. When compiling the wrapper file, be sure to
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| 31 | -- reference the XilinxCoreLib VHDL simulation library. For detailed
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| 32 | -- instructions, please refer to the "CORE Generator Help".
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| 33 |
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| 34 | -- The synthesis directives "translate_off/translate_on" specified
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| 35 | -- below are supported by Xilinx, Mentor Graphics and Synplicity
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| 36 | -- synthesis tools. Ensure they are correct for your synthesis tool(s).
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| 37 |
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| 38 | LIBRARY ieee;
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| 39 | USE ieee.std_logic_1164.ALL;
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| 40 | -- synthesis translate_off
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| 41 | Library XilinxCoreLib;
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| 42 | -- synthesis translate_on
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| 43 | ENTITY adder_5_bits IS
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| 44 | port (
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| 45 | a: IN std_logic_VECTOR(4 downto 0);
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| 46 | b: IN std_logic_VECTOR(4 downto 0);
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| 47 | clk: IN std_logic;
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| 48 | s: OUT std_logic_VECTOR(5 downto 0));
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| 49 | END adder_5_bits;
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| 50 |
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| 51 | ARCHITECTURE adder_5_bits_a OF adder_5_bits IS
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| 52 | -- synthesis translate_off
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| 53 | component wrapped_adder_5_bits
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| 54 | port (
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| 55 | a: IN std_logic_VECTOR(4 downto 0);
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| 56 | b: IN std_logic_VECTOR(4 downto 0);
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| 57 | clk: IN std_logic;
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| 58 | s: OUT std_logic_VECTOR(5 downto 0));
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| 59 | end component;
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| 60 |
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| 61 | -- Configuration specification
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| 62 | for all : wrapped_adder_5_bits use entity XilinxCoreLib.c_addsub_v11_0(behavioral)
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| 63 | generic map(
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| 64 | c_a_width => 5,
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| 65 | c_out_width => 6,
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| 66 | c_add_mode => 0,
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| 67 | c_has_c_out => 0,
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| 68 | c_b_type => 1,
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| 69 | c_borrow_low => 1,
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| 70 | c_ce_overrides_sclr => 0,
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| 71 | c_implementation => 0,
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| 72 | c_has_sclr => 0,
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| 73 | c_verbosity => 0,
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| 74 | c_latency => 1,
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| 75 | c_has_bypass => 0,
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| 76 | c_ainit_val => "0",
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| 77 | c_bypass_low => 0,
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| 78 | c_has_ce => 0,
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| 79 | c_sclr_overrides_sset => 0,
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| 80 | c_sinit_val => "0",
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| 81 | c_has_sset => 0,
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| 82 | c_has_c_in => 0,
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| 83 | c_has_sinit => 0,
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| 84 | c_b_constant => 0,
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| 85 | c_ce_overrides_bypass => 1,
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| 86 | c_xdevicefamily => "spartan3adsp",
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| 87 | c_a_type => 1,
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| 88 | c_b_width => 5,
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| 89 | c_b_value => "00000");
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| 90 | -- synthesis translate_on
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| 91 | BEGIN
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| 92 | -- synthesis translate_off
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| 93 | U0 : wrapped_adder_5_bits
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| 94 | port map (
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| 95 | a => a,
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| 96 | b => b,
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| 97 | clk => clk,
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| 98 | s => s);
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| 99 | -- synthesis translate_on
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| 100 |
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| 101 | END adder_5_bits_a;
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| 102 |
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