source: firmware/FTM/trigger/drivers/detection_logic/adder_5_bits.vhd@ 10366

Last change on this file since 10366 was 10366, checked in by weitzel, 10 years ago
FTM trigger manager from MCSE added; DCM arrangement changed; changes in FTM ethernet module
File size: 4.1 KB
Line 
1--------------------------------------------------------------------------------
2-- This file is owned and controlled by Xilinx and must be used --
3-- solely for design, simulation, implementation and creation of --
4-- design files limited to Xilinx devices or technologies. Use --
5-- with non-Xilinx devices or technologies is expressly prohibited --
6-- and immediately terminates your license. --
7-- --
8-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
9-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
10-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
11-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
12-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
13-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
14-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
15-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
16-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
17-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
18-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
19-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
20-- FOR A PARTICULAR PURPOSE. --
21-- --
22-- Xilinx products are not intended for use in life support --
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24-- expressly prohibited. --
25-- --
26-- (c) Copyright 1995-2009 Xilinx, Inc. --
27-- All rights reserved. --
28--------------------------------------------------------------------------------
29-- You must compile the wrapper file adder_5_bits.vhd when simulating
30-- the core, adder_5_bits. When compiling the wrapper file, be sure to
31-- reference the XilinxCoreLib VHDL simulation library. For detailed
32-- instructions, please refer to the "CORE Generator Help".
33
34-- The synthesis directives "translate_off/translate_on" specified
35-- below are supported by Xilinx, Mentor Graphics and Synplicity
36-- synthesis tools. Ensure they are correct for your synthesis tool(s).
37
38LIBRARY ieee;
39USE ieee.std_logic_1164.ALL;
40-- synthesis translate_off
41Library XilinxCoreLib;
42-- synthesis translate_on
43ENTITY adder_5_bits IS
44 port (
45 a: IN std_logic_VECTOR(4 downto 0);
46 b: IN std_logic_VECTOR(4 downto 0);
47 clk: IN std_logic;
48 s: OUT std_logic_VECTOR(5 downto 0));
49END adder_5_bits;
50
51ARCHITECTURE adder_5_bits_a OF adder_5_bits IS
52-- synthesis translate_off
53component wrapped_adder_5_bits
54 port (
55 a: IN std_logic_VECTOR(4 downto 0);
56 b: IN std_logic_VECTOR(4 downto 0);
57 clk: IN std_logic;
58 s: OUT std_logic_VECTOR(5 downto 0));
59end component;
60
61-- Configuration specification
62 for all : wrapped_adder_5_bits use entity XilinxCoreLib.c_addsub_v11_0(behavioral)
63 generic map(
64 c_a_width => 5,
65 c_out_width => 6,
66 c_add_mode => 0,
67 c_has_c_out => 0,
68 c_b_type => 1,
69 c_borrow_low => 1,
70 c_ce_overrides_sclr => 0,
71 c_implementation => 0,
72 c_has_sclr => 0,
73 c_verbosity => 0,
74 c_latency => 1,
75 c_has_bypass => 0,
76 c_ainit_val => "0",
77 c_bypass_low => 0,
78 c_has_ce => 0,
79 c_sclr_overrides_sset => 0,
80 c_sinit_val => "0",
81 c_has_sset => 0,
82 c_has_c_in => 0,
83 c_has_sinit => 0,
84 c_b_constant => 0,
85 c_ce_overrides_bypass => 1,
86 c_xdevicefamily => "spartan3adsp",
87 c_a_type => 1,
88 c_b_width => 5,
89 c_b_value => "00000");
90-- synthesis translate_on
91BEGIN
92-- synthesis translate_off
93U0 : wrapped_adder_5_bits
94 port map (
95 a => a,
96 b => b,
97 clk => clk,
98 s => s);
99-- synthesis translate_on
100
101END adder_5_bits_a;
102
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