source: firmware/FTM/trigger/drivers/detection_logic/trigger_sum.vhd@ 19744

Last change on this file since 19744 was 10366, checked in by weitzel, 15 years ago
FTM trigger manager from MCSE added; DCM arrangement changed; changes in FTM ethernet module
File size: 5.8 KB
Line 
1--=======================================================================================
2-- TITLE : Sum of physics or calibration triggers
3-- DESCRIPTION : Convert number of inputs to '1' on 40bits to a sum on 6bits.
4-- FILE : trigger_sum.vhd
5-- COMPANY : Micro-Cameras & Space Exploration SA
6--=======================================================================================
7-- CREATION
8-- DATE AUTHOR PROJECT REVISION
9-- 07/03/2011 JGi 110307a
10--=======================================================================================
11-- MODIFICATION HISTORY
12-- DATE AUTHOR PROJECT REVISION COMMENTS
13-- 07/03/2011 JGi 110307a Description
14--=======================================================================================
15-- Library Definition
16library ieee;
17 use ieee.std_logic_1164.all;
18 use ieee.numeric_std.all;
19
20-- Entity Definition
21entity trigger_sum is
22 port( --clk
23 clk_250MHz : in std_logic;
24 --inputs
25 trig_window_0 : in std_logic_vector(9 downto 0);
26 trig_window_1 : in std_logic_vector(9 downto 0);
27 trig_window_2 : in std_logic_vector(9 downto 0);
28 trig_window_3 : in std_logic_vector(9 downto 0);
29 --output
30 number_of_events : out std_logic_vector(5 downto 0));
31end trigger_sum;
32
33-- Architecture Definition
34architecture RTL of trigger_sum is
35
36 component unary_to_binary is
37 port( clk_250MHz : in std_logic;
38 vector_in : in std_logic_vector(4 downto 0);
39 result : out std_logic_vector(2 downto 0));
40 end component;
41
42 signal i_bin_to_dec_result_0 : std_logic_vector(2 downto 0);
43 signal i_bin_to_dec_result_1 : std_logic_vector(2 downto 0);
44 signal i_bin_to_dec_result_2 : std_logic_vector(2 downto 0);
45 signal i_bin_to_dec_result_3 : std_logic_vector(2 downto 0);
46 signal i_bin_to_dec_result_4 : std_logic_vector(2 downto 0);
47 signal i_bin_to_dec_result_5 : std_logic_vector(2 downto 0);
48 signal i_bin_to_dec_result_6 : std_logic_vector(2 downto 0);
49 signal i_bin_to_dec_result_7 : std_logic_vector(2 downto 0);
50
51 component adder_3_bits is
52 port( a : in std_logic_vector(2 downto 0);
53 b : in std_logic_vector(2 downto 0);
54 clk : in std_logic;
55 s : out std_logic_vector(3 downto 0));
56 end component;
57
58 signal i_add_3_bits_result_0 : std_logic_vector(3 downto 0);
59 signal i_add_3_bits_result_1 : std_logic_vector(3 downto 0);
60 signal i_add_3_bits_result_2 : std_logic_vector(3 downto 0);
61 signal i_add_3_bits_result_3 : std_logic_vector(3 downto 0);
62
63 component adder_4_bits is
64 port( a : in std_logic_vector(3 downto 0);
65 b : in std_logic_vector(3 downto 0);
66 clk : in std_logic;
67 s : out std_logic_vector(4 downto 0));
68 end component;
69
70 signal i_add_4_bits_result_0 : std_logic_vector(4 downto 0);
71 signal i_add_4_bits_result_1 : std_logic_vector(4 downto 0);
72
73 component adder_5_bits is
74 port( a : in std_logic_vector(4 downto 0);
75 b : in std_logic_vector(4 downto 0);
76 clk : in std_logic;
77 s : out std_logic_vector(5 downto 0));
78 end component;
79
80begin
81
82 -- Component instantiation
83 -- Binary to decimal
84 bin_to_dec_0: unary_to_binary
85 port map( clk_250MHz => clk_250MHz,
86 vector_in => trig_window_0(4 downto 0),
87 result => i_bin_to_dec_result_0);
88
89 bin_to_dec_1: unary_to_binary
90 port map( clk_250MHz => clk_250MHz,
91 vector_in => trig_window_0(9 downto 5),
92 result => i_bin_to_dec_result_1);
93
94 bin_to_dec_2: unary_to_binary
95 port map( clk_250MHz => clk_250MHz,
96 vector_in => trig_window_1(4 downto 0),
97 result => i_bin_to_dec_result_2);
98
99 bin_to_dec_3: unary_to_binary
100 port map( clk_250MHz => clk_250MHz,
101 vector_in => trig_window_1(9 downto 5),
102 result => i_bin_to_dec_result_3);
103
104 bin_to_dec_4: unary_to_binary
105 port map( clk_250MHz => clk_250MHz,
106 vector_in => trig_window_2(4 downto 0),
107 result => i_bin_to_dec_result_4);
108
109 bin_to_dec_5: unary_to_binary
110 port map( clk_250MHz => clk_250MHz,
111 vector_in => trig_window_2(9 downto 5),
112 result => i_bin_to_dec_result_5);
113
114 bin_to_dec_6: unary_to_binary
115 port map( clk_250MHz => clk_250MHz,
116 vector_in => trig_window_3(4 downto 0),
117 result => i_bin_to_dec_result_6);
118
119 bin_to_dec_7: unary_to_binary
120 port map( clk_250MHz => clk_250MHz,
121 vector_in => trig_window_3(9 downto 5),
122 result => i_bin_to_dec_result_7);
123
124 -- 3 bits adders
125 inst_3_bits_add_0: adder_3_bits
126 port map( clk => clk_250MHz,
127 a => i_bin_to_dec_result_0,
128 b => i_bin_to_dec_result_1,
129 s => i_add_3_bits_result_0);
130
131 inst_3_bits_add_1: adder_3_bits
132 port map( clk => clk_250MHz,
133 a => i_bin_to_dec_result_2,
134 b => i_bin_to_dec_result_3,
135 s => i_add_3_bits_result_1);
136
137 inst_3_bits_add_2: adder_3_bits
138 port map( clk => clk_250MHz,
139 a => i_bin_to_dec_result_4,
140 b => i_bin_to_dec_result_5,
141 s => i_add_3_bits_result_2);
142
143 inst_3_bits_add_3: adder_3_bits
144 port map( clk => clk_250MHz,
145 a => i_bin_to_dec_result_6,
146 b => i_bin_to_dec_result_7,
147 s => i_add_3_bits_result_3);
148
149 -- 4 bits adders
150 inst_4_bits_add_0: adder_4_bits
151 port map( clk => clk_250MHz,
152 a => i_add_3_bits_result_0,
153 b => i_add_3_bits_result_1,
154 s => i_add_4_bits_result_0);
155
156 inst_4_bits_add_1: adder_4_bits
157 port map( clk => clk_250MHz,
158 a => i_add_3_bits_result_2,
159 b => i_add_3_bits_result_3,
160 s => i_add_4_bits_result_1);
161
162 ---- Final 5 bits adders
163 inst_5_bits_add_0: adder_5_bits
164 port map( clk => clk_250MHz,
165 a => i_add_4_bits_result_0,
166 b => i_add_4_bits_result_1,
167 s => number_of_events);
168
169end RTL;
Note: See TracBrowser for help on using the repository browser.