source: firmware/FTM/trigger/drivers/input_synch/input_synch.vhd@ 15744

Last change on this file since 15744 was 10366, checked in by weitzel, 15 years ago
FTM trigger manager from MCSE added; DCM arrangement changed; changes in FTM ethernet module
File size: 9.5 KB
Line 
1--=======================================================================================
2-- TITLE : Input synchronization block
3-- DESCRIPTION : Synchronization of FTUs signals using FPGA DDR input registers
4-- FILE : input_synch.vhd
5-- COMPANY : Micro-Cameras & Space Exploration SA
6--=======================================================================================
7-- CREATION
8-- DATE AUTHOR PROJECT REVISION
9-- 02/03/2011 JGi FTM 110302a
10--=======================================================================================
11-- MODIFICATION HISTORY
12-- DATE AUTHOR PROJECT REVISION COMMENTS
13-- 02/03/2011 JGi FTM 110302a Description
14--=======================================================================================
15-- Library Definition
16library ieee;
17 use ieee.std_logic_1164.all;
18 use ieee.std_logic_arith.all;
19 use ieee.std_logic_unsigned.all;
20
21library unisim;
22 use unisim.vcomponents.all;
23
24-- Entity Definition
25entity input_synch is
26 port( --clock
27 clk_250MHz : in std_logic;
28 clk_250MHz_180 : in std_logic;
29 --trigger primitives from FTUs
30 trig_prim_0 : in std_logic_vector(9 downto 0); --crate 0
31 trig_prim_1 : in std_logic_vector(9 downto 0); --crate 1
32 trig_prim_2 : in std_logic_vector(9 downto 0); --crate 2
33 trig_prim_3 : in std_logic_vector(9 downto 0); --crate 3
34 --synchronized trigger primitives
35 trig_synch_0_rise : out std_logic_vector(9 downto 0); --crate 0
36 trig_synch_1_rise : out std_logic_vector(9 downto 0); --crate 1
37 trig_synch_2_rise : out std_logic_vector(9 downto 0); --crate 2
38 trig_synch_3_rise : out std_logic_vector(9 downto 0); --crate 3
39 trig_synch_0_fall : out std_logic_vector(9 downto 0); --crate 0
40 trig_synch_1_fall : out std_logic_vector(9 downto 0); --crate 1
41 trig_synch_2_fall : out std_logic_vector(9 downto 0); --crate 2
42 trig_synch_3_fall : out std_logic_vector(9 downto 0)); --crate 3
43end input_synch;
44
45-- Architecture Definition
46architecture RTL of input_synch is
47
48 type t_reg is record
49 -- Internal register declaration
50 -- Ouput register declaration
51 trig_synch_0_rise : std_logic_vector(9 downto 0);
52 trig_synch_1_rise : std_logic_vector(9 downto 0);
53 trig_synch_2_rise : std_logic_vector(9 downto 0);
54 trig_synch_3_rise : std_logic_vector(9 downto 0);
55 trig_synch_0_fall : std_logic_vector(9 downto 0);
56 trig_synch_1_fall : std_logic_vector(9 downto 0);
57 trig_synch_2_fall : std_logic_vector(9 downto 0);
58 trig_synch_3_fall : std_logic_vector(9 downto 0);
59 end record;
60
61 signal i_trig_synch_0_rise : std_logic_vector(9 downto 0) := (others => '0');
62 signal i_trig_synch_1_rise : std_logic_vector(9 downto 0) := (others => '0');
63 signal i_trig_synch_2_rise : std_logic_vector(9 downto 0) := (others => '0');
64 signal i_trig_synch_3_rise : std_logic_vector(9 downto 0) := (others => '0');
65 signal i_trig_synch_0_fall : std_logic_vector(9 downto 0) := (others => '0');
66 signal i_trig_synch_1_fall : std_logic_vector(9 downto 0) := (others => '0');
67 signal i_trig_synch_2_fall : std_logic_vector(9 downto 0) := (others => '0');
68 signal i_trig_synch_3_fall : std_logic_vector(9 downto 0) := (others => '0');
69
70 signal i_next_reg : t_reg := (trig_synch_0_rise => (others => '0'),
71 trig_synch_1_rise => (others => '0'),
72 trig_synch_2_rise => (others => '0'),
73 trig_synch_3_rise => (others => '0'),
74 trig_synch_0_fall => (others => '0'),
75 trig_synch_1_fall => (others => '0'),
76 trig_synch_2_fall => (others => '0'),
77 trig_synch_3_fall => (others => '0'));
78 signal i_reg : t_reg := (trig_synch_0_rise => (others => '0'),
79 trig_synch_1_rise => (others => '0'),
80 trig_synch_2_rise => (others => '0'),
81 trig_synch_3_rise => (others => '0'),
82 trig_synch_0_fall => (others => '0'),
83 trig_synch_1_fall => (others => '0'),
84 trig_synch_2_fall => (others => '0'),
85 trig_synch_3_fall => (others => '0'));
86
87begin
88
89 -- Input DDR flip-flops instantiation for crate 0
90 input_ddr_0: for i in 0 to 9 generate
91 iddr2_inst_trig_synch_0 : IDDR2
92 generic map(DDR_ALIGNMENT => "NONE", -- sets output alignment to "none", "c0", "c1"
93 INIT_Q0 => '0', -- sets initial state of the q0 output to '0' or '1'
94 INIT_Q1 => '0', -- sets initial state of the q1 output to '0' or '1'
95 SRTYPE => "SYNC") -- specifies "sync" or "async" set/reset
96 port map( Q0 => i_trig_synch_0_rise(i), -- 1-bit output captured with c0 clock
97 Q1 => i_trig_synch_0_fall(i), -- 1-bit output captured with c1 clock
98 C0 => clk_250mhz, -- 1-bit clock input
99 C1 => clk_250mhz_180, -- 1-bit clock input
100 CE => '1', -- 1-bit clock enable input
101 D => trig_prim_0(i), -- 1-bit data input
102 R => '0', -- 1-bit reset input
103 S => '0'); -- 1-bit set input
104 end generate input_ddr_0;
105
106 -- Input DDR flip-flops instantiation for crate 1
107 input_ddr_1: for i in 0 to 9 generate
108 iddr2_inst_trig_synch_1 : IDDR2
109 generic map(DDR_ALIGNMENT => "NONE",
110 INIT_Q0 => '0',
111 INIT_Q1 => '0',
112 SRTYPE => "SYNC")
113 port map( Q0 => i_trig_synch_1_rise(i),
114 Q1 => i_trig_synch_1_fall(i),
115 C0 => clk_250mhz,
116 C1 => clk_250mhz_180,
117 CE => '1',
118 D => trig_prim_1(i),
119 R => '0',
120 S => '0');
121 end generate input_ddr_1;
122
123 -- Input DDR flip-flops instantiation for crate 2
124 input_ddr_2: for i in 0 to 9 generate
125 iddr2_inst_trig_synch_2 : IDDR2
126 generic map(DDR_ALIGNMENT => "NONE",
127 INIT_Q0 => '0',
128 INIT_Q1 => '0',
129 SRTYPE => "SYNC")
130 port map( Q0 => i_trig_synch_2_rise(i),
131 Q1 => i_trig_synch_2_fall(i),
132 C0 => clk_250mhz,
133 C1 => clk_250mhz_180,
134 CE => '1',
135 D => trig_prim_2(i),
136 R => '0',
137 S => '0');
138 end generate input_ddr_2;
139
140 -- Input DDR flip-flops instantiation for crate 3
141 input_ddr_3: for i in 0 to 9 generate
142 iddr2_inst_trig_synch_3 : IDDR2
143 generic map(DDR_ALIGNMENT => "NONE",
144 INIT_Q0 => '0',
145 INIT_Q1 => '0',
146 SRTYPE => "SYNC")
147 port map( Q0 => i_trig_synch_3_rise(i),
148 Q1 => i_trig_synch_3_fall(i),
149 C0 => clk_250mhz,
150 C1 => clk_250mhz_180,
151 CE => '1',
152 D => trig_prim_3(i),
153 R => '0',
154 S => '0');
155 end generate input_ddr_3;
156
157 -- Combinatorial logic
158 process(i_trig_synch_0_rise, i_trig_synch_1_rise, i_trig_synch_2_rise,
159 i_trig_synch_3_rise, i_trig_synch_0_fall, i_trig_synch_1_fall,
160 i_trig_synch_2_fall, i_trig_synch_3_fall, i_reg)
161 variable v_reg : t_reg := (trig_synch_0_rise => (others => '0'),
162 trig_synch_1_rise => (others => '0'),
163 trig_synch_2_rise => (others => '0'),
164 trig_synch_3_rise => (others => '0'),
165 trig_synch_0_fall => (others => '0'),
166 trig_synch_1_fall => (others => '0'),
167 trig_synch_2_fall => (others => '0'),
168 trig_synch_3_fall => (others => '0'));
169 begin
170 v_reg := i_reg;
171 --===================================================================================
172
173 --===================================================================================
174 -- Delay management for rising edge data
175 --===================================================================================
176 v_reg.trig_synch_0_rise := i_trig_synch_0_rise;
177 v_reg.trig_synch_1_rise := i_trig_synch_1_rise;
178 v_reg.trig_synch_2_rise := i_trig_synch_2_rise;
179 v_reg.trig_synch_3_rise := i_trig_synch_3_rise;
180 --===================================================================================
181
182 --===================================================================================
183 -- Delay management for falling edge data
184 --===================================================================================
185 v_reg.trig_synch_0_fall := i_trig_synch_0_fall;
186 v_reg.trig_synch_1_fall := i_trig_synch_1_fall;
187 v_reg.trig_synch_2_fall := i_trig_synch_2_fall;
188 v_reg.trig_synch_3_fall := i_trig_synch_3_fall;
189 --===================================================================================
190
191 --===================================================================================
192 -- Drive register input
193 i_next_reg <= v_reg;
194
195 --===================================================================================
196 -- Output assignation
197 trig_synch_0_rise <= i_reg.trig_synch_0_rise;
198 trig_synch_1_rise <= i_reg.trig_synch_1_rise;
199 trig_synch_2_rise <= i_reg.trig_synch_2_rise;
200 trig_synch_3_rise <= i_reg.trig_synch_3_rise;
201 trig_synch_0_fall <= i_reg.trig_synch_0_fall;
202 trig_synch_1_fall <= i_reg.trig_synch_1_fall;
203 trig_synch_2_fall <= i_reg.trig_synch_2_fall;
204 trig_synch_3_fall <= i_reg.trig_synch_3_fall;
205 --===================================================================================
206 end process;
207
208 -- Sequential logic
209 process(clk_250MHz)
210 begin
211 if rising_edge(clk_250MHz) then
212 i_reg <= i_next_reg;
213 end if;
214 end process;
215
216end RTL;
Note: See TracBrowser for help on using the repository browser.