source: firmware/FTM/trigger/drivers/interface_sync/interface_sync_250MHz.vhd@ 10366

Last change on this file since 10366 was 10366, checked in by weitzel, 15 years ago
FTM trigger manager from MCSE added; DCM arrangement changed; changes in FTM ethernet module
File size: 16.3 KB
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1--=======================================================================================
2-- TITLE : Interface synchronization to 250MHz
3-- DESCRIPTION : Synchronize incoming settings to the 250MHz clock
4-- FILE : interface_sync_250MHz.vhd
5-- COMPANY : Micro-Cameras & Space Exploration SA
6--=======================================================================================
7-- CREATION
8-- DATE AUTHOR PROJECT REVISION
9-- 11/03/2011 JGi 110311a
10--=======================================================================================
11-- MODIFICATION HISTORY
12-- DATE AUTHOR PROJECT REVISION COMMENTS
13-- 11/03/2011 JGi 110311a Description
14--=======================================================================================
15-- Library Definition
16library ieee;
17 use ieee.std_logic_1164.all;
18 use ieee.numeric_std.all;
19
20-- Entity Definition
21entity interface_sync_250MHz is
22 port( --clock
23 clk_250MHz : in std_logic;
24 --inputs
25 start_run : in std_logic;
26 stop_run : in std_logic;
27 new_config : in std_logic;
28 general_settings : in std_logic_vector(15 downto 0);
29 LP_and_PED_freq : in std_logic_vector(15 downto 0);
30 LP1_LP2_PED_ratio : in std_logic_vector(15 downto 0);
31 maj_coinc_n_phys : in std_logic_vector(15 downto 0);
32 maj_coinc_n_calib : in std_logic_vector(15 downto 0);
33 trigger_delay : in std_logic_vector(15 downto 0);
34 TIM_delay : in std_logic_vector(15 downto 0);
35 dead_time : in std_logic_vector(15 downto 0);
36 coinc_window_phys : in std_logic_vector(15 downto 0);
37 coinc_window_calib : in std_logic_vector(15 downto 0);
38 active_FTU_list_0 : in std_logic_vector(15 downto 0);
39 active_FTU_list_1 : in std_logic_vector(15 downto 0);
40 active_FTU_list_2 : in std_logic_vector(15 downto 0);
41 active_FTU_list_3 : in std_logic_vector(15 downto 0);
42 --outputs
43 config_done : out std_logic;
44 sync_start_run : out std_logic;
45 sync_stop_run : out std_logic;
46 sync_general_settings : out std_logic_vector(7 downto 0);
47 sync_LP_and_PED_freq : out std_logic_vector(9 downto 0);
48 sync_LP1_LP2_PED_ratio : out std_logic_vector(14 downto 0);
49 sync_maj_coinc_n_phys : out std_logic_vector(5 downto 0);
50 sync_maj_coinc_n_calib : out std_logic_vector(5 downto 0);
51 sync_trigger_delay : out std_logic_vector(9 downto 0);
52 sync_TIM_delay : out std_logic_vector(9 downto 0);
53 sync_dead_time : out std_logic_vector(15 downto 0);
54 sync_coinc_window_phys : out std_logic_vector(3 downto 0);
55 sync_coinc_window_calib : out std_logic_vector(3 downto 0);
56 sync_active_FTU_list_0 : out std_logic_vector(9 downto 0);
57 sync_active_FTU_list_1 : out std_logic_vector(9 downto 0);
58 sync_active_FTU_list_2 : out std_logic_vector(9 downto 0);
59 sync_active_FTU_list_3 : out std_logic_vector(9 downto 0));
60end interface_sync_250MHz;
61
62-- Architecture Definition
63architecture RTL of interface_sync_250MHz is
64
65 type t_reg is record
66 -- Internal register declaration
67 -- Ouput register declaration
68 config_done : std_logic_vector(1 downto 0);
69 sync_0_start_run : std_logic;
70 sync_1_start_run : std_logic;
71 sync_0_stop_run : std_logic;
72 sync_1_stop_run : std_logic;
73 sync_0_new_config : std_logic;
74 sync_1_new_config : std_logic;
75 sync_0_general_settings : std_logic_vector(7 downto 0);
76 sync_1_general_settings : std_logic_vector(7 downto 0);
77 sync_0_LP_and_PED_freq : std_logic_vector(9 downto 0);
78 sync_1_LP_and_PED_freq : std_logic_vector(9 downto 0);
79 sync_0_LP1_LP2_PED_ratio : std_logic_vector(14 downto 0);
80 sync_1_LP1_LP2_PED_ratio : std_logic_vector(14 downto 0);
81 sync_0_maj_coinc_n_phys : std_logic_vector(5 downto 0);
82 sync_1_maj_coinc_n_phys : std_logic_vector(5 downto 0);
83 sync_0_maj_coinc_n_calib : std_logic_vector(5 downto 0);
84 sync_1_maj_coinc_n_calib : std_logic_vector(5 downto 0);
85 sync_0_trigger_delay : std_logic_vector(9 downto 0);
86 sync_1_trigger_delay : std_logic_vector(9 downto 0);
87 sync_0_TIM_delay : std_logic_vector(9 downto 0);
88 sync_1_TIM_delay : std_logic_vector(9 downto 0);
89 sync_0_dead_time : std_logic_vector(15 downto 0);
90 sync_1_dead_time : std_logic_vector(15 downto 0);
91 sync_0_coinc_window_phys : std_logic_vector(3 downto 0);
92 sync_1_coinc_window_phys : std_logic_vector(3 downto 0);
93 sync_0_coinc_window_calib : std_logic_vector(3 downto 0);
94 sync_1_coinc_window_calib : std_logic_vector(3 downto 0);
95 sync_0_active_FTU_list_0 : std_logic_vector(9 downto 0);
96 sync_1_active_FTU_list_0 : std_logic_vector(9 downto 0);
97 sync_0_active_FTU_list_1 : std_logic_vector(9 downto 0);
98 sync_1_active_FTU_list_1 : std_logic_vector(9 downto 0);
99 sync_0_active_FTU_list_2 : std_logic_vector(9 downto 0);
100 sync_1_active_FTU_list_2 : std_logic_vector(9 downto 0);
101 sync_0_active_FTU_list_3 : std_logic_vector(9 downto 0);
102 sync_1_active_FTU_list_3 : std_logic_vector(9 downto 0);
103 end record;
104
105 signal i_next_reg : t_reg := (config_done => (others => '0'),
106 sync_0_start_run => '0',
107 sync_1_start_run => '0',
108 sync_0_stop_run => '0',
109 sync_1_stop_run => '0',
110 sync_0_new_config => '0',
111 sync_1_new_config => '0',
112 sync_0_general_settings => (others => '0'),
113 sync_1_general_settings => (others => '0'),
114 sync_0_LP_and_PED_freq => (others => '0'),
115 sync_1_LP_and_PED_freq => (others => '0'),
116 sync_0_LP1_LP2_PED_ratio => (others => '0'),
117 sync_1_LP1_LP2_PED_ratio => (others => '0'),
118 sync_0_maj_coinc_n_phys => (others => '1'),
119 sync_1_maj_coinc_n_phys => (others => '1'),
120 sync_0_maj_coinc_n_calib => (others => '1'),
121 sync_1_maj_coinc_n_calib => (others => '1'),
122 sync_0_trigger_delay => (others => '0'),
123 sync_1_trigger_delay => (others => '0'),
124 sync_0_TIM_delay => (others => '0'),
125 sync_1_TIM_delay => (others => '0'),
126 sync_0_dead_time => (others => '0'),
127 sync_1_dead_time => (others => '0'),
128 sync_0_coinc_window_phys => (others => '0'),
129 sync_1_coinc_window_phys => (others => '0'),
130 sync_0_coinc_window_calib => (others => '0'),
131 sync_1_coinc_window_calib => (others => '0'),
132 sync_0_active_FTU_list_0 => (others => '0'),
133 sync_1_active_FTU_list_0 => (others => '0'),
134 sync_0_active_FTU_list_1 => (others => '0'),
135 sync_1_active_FTU_list_1 => (others => '0'),
136 sync_0_active_FTU_list_2 => (others => '0'),
137 sync_1_active_FTU_list_2 => (others => '0'),
138 sync_0_active_FTU_list_3 => (others => '0'),
139 sync_1_active_FTU_list_3 => (others => '0'));
140 signal i_reg : t_reg := (config_done => (others => '0'),
141 sync_0_start_run => '0',
142 sync_1_start_run => '0',
143 sync_0_stop_run => '0',
144 sync_1_stop_run => '0',
145 sync_0_new_config => '0',
146 sync_1_new_config => '0',
147 sync_0_general_settings => (others => '0'),
148 sync_1_general_settings => (others => '0'),
149 sync_0_LP_and_PED_freq => (others => '0'),
150 sync_1_LP_and_PED_freq => (others => '0'),
151 sync_0_LP1_LP2_PED_ratio => (others => '0'),
152 sync_1_LP1_LP2_PED_ratio => (others => '0'),
153 sync_0_maj_coinc_n_phys => (others => '1'),
154 sync_1_maj_coinc_n_phys => (others => '1'),
155 sync_0_maj_coinc_n_calib => (others => '1'),
156 sync_1_maj_coinc_n_calib => (others => '1'),
157 sync_0_trigger_delay => (others => '0'),
158 sync_1_trigger_delay => (others => '0'),
159 sync_0_TIM_delay => (others => '0'),
160 sync_1_TIM_delay => (others => '0'),
161 sync_0_dead_time => (others => '0'),
162 sync_1_dead_time => (others => '0'),
163 sync_0_coinc_window_phys => (others => '0'),
164 sync_1_coinc_window_phys => (others => '0'),
165 sync_0_coinc_window_calib => (others => '0'),
166 sync_1_coinc_window_calib => (others => '0'),
167 sync_0_active_FTU_list_0 => (others => '0'),
168 sync_1_active_FTU_list_0 => (others => '0'),
169 sync_0_active_FTU_list_1 => (others => '0'),
170 sync_1_active_FTU_list_1 => (others => '0'),
171 sync_0_active_FTU_list_2 => (others => '0'),
172 sync_1_active_FTU_list_2 => (others => '0'),
173 sync_0_active_FTU_list_3 => (others => '0'),
174 sync_1_active_FTU_list_3 => (others => '0'));
175
176begin
177
178 -- Component instantiation
179
180 -- Combinatorial logic
181 process(start_run, stop_run, new_config, general_settings, LP_and_PED_freq,
182 LP1_LP2_PED_ratio, maj_coinc_n_phys, maj_coinc_n_calib, trigger_delay,
183 TIM_delay, dead_time, coinc_window_phys, coinc_window_calib, active_FTU_list_0,
184 active_FTU_list_1, active_FTU_list_2, active_FTU_list_3, i_reg)
185 variable v_reg : t_reg := (config_done => (others => '0'),
186 sync_0_start_run => '0',
187 sync_1_start_run => '0',
188 sync_0_stop_run => '0',
189 sync_1_stop_run => '0',
190 sync_0_new_config => '0',
191 sync_1_new_config => '0',
192 sync_0_general_settings => (others => '0'),
193 sync_1_general_settings => (others => '0'),
194 sync_0_LP_and_PED_freq => (others => '0'),
195 sync_1_LP_and_PED_freq => (others => '0'),
196 sync_0_LP1_LP2_PED_ratio => (others => '0'),
197 sync_1_LP1_LP2_PED_ratio => (others => '0'),
198 sync_0_maj_coinc_n_phys => (others => '1'),
199 sync_1_maj_coinc_n_phys => (others => '1'),
200 sync_0_maj_coinc_n_calib => (others => '1'),
201 sync_1_maj_coinc_n_calib => (others => '1'),
202 sync_0_trigger_delay => (others => '0'),
203 sync_1_trigger_delay => (others => '0'),
204 sync_0_TIM_delay => (others => '0'),
205 sync_1_TIM_delay => (others => '0'),
206 sync_0_dead_time => (others => '0'),
207 sync_1_dead_time => (others => '0'),
208 sync_0_coinc_window_phys => (others => '0'),
209 sync_1_coinc_window_phys => (others => '0'),
210 sync_0_coinc_window_calib => (others => '0'),
211 sync_1_coinc_window_calib => (others => '0'),
212 sync_0_active_FTU_list_0 => (others => '0'),
213 sync_1_active_FTU_list_0 => (others => '0'),
214 sync_0_active_FTU_list_1 => (others => '0'),
215 sync_1_active_FTU_list_1 => (others => '0'),
216 sync_0_active_FTU_list_2 => (others => '0'),
217 sync_1_active_FTU_list_2 => (others => '0'),
218 sync_0_active_FTU_list_3 => (others => '0'),
219 sync_1_active_FTU_list_3 => (others => '0'));
220 begin
221 v_reg := i_reg;
222 --===================================================================================
223
224 --===================================================================================
225 -- Double synchronization of incoming signals
226 --===================================================================================
227 -- Double synchonize command signals
228 v_reg.sync_0_start_run := start_run;
229 v_reg.sync_1_start_run := i_reg.sync_0_start_run;
230 v_reg.sync_0_stop_run := stop_run;
231 v_reg.sync_1_stop_run := i_reg.sync_0_stop_run;
232 v_reg.sync_0_new_config := new_config;
233 v_reg.sync_1_new_config := i_reg.sync_0_new_config;
234
235 v_reg.config_done(0) := '0';
236 v_reg.config_done(1) := i_reg.config_done(0);
237
238 -- If new configuration is received, register settings
239 if i_reg.sync_1_new_config = '1' then
240 v_reg.config_done(0) := '1';
241 v_reg.sync_0_general_settings := general_settings(7 downto 0);
242 v_reg.sync_0_LP_and_PED_freq := LP_and_PED_freq(9 downto 0);
243 v_reg.sync_0_LP1_LP2_PED_ratio := LP1_LP2_PED_ratio(14 downto 0);
244 v_reg.sync_0_maj_coinc_n_phys := maj_coinc_n_phys(5 downto 0);
245 v_reg.sync_0_maj_coinc_n_calib := maj_coinc_n_calib(5 downto 0);
246 v_reg.sync_0_trigger_delay := trigger_delay(9 downto 0);
247 v_reg.sync_0_TIM_delay := TIM_delay(9 downto 0);
248 v_reg.sync_0_dead_time := dead_time(15 downto 0);
249 v_reg.sync_0_coinc_window_phys := coinc_window_phys(3 downto 0);
250 v_reg.sync_0_coinc_window_calib := coinc_window_calib(3 downto 0);
251 v_reg.sync_0_active_FTU_list_0 := active_FTU_list_0(9 downto 0);
252 v_reg.sync_0_active_FTU_list_1 := active_FTU_list_1(9 downto 0);
253 v_reg.sync_0_active_FTU_list_2 := active_FTU_list_2(9 downto 0);
254 v_reg.sync_0_active_FTU_list_3 := active_FTU_list_3(9 downto 0);
255 end if;
256 v_reg.sync_1_general_settings := i_reg.sync_0_general_settings;
257 v_reg.sync_1_LP_and_PED_freq := i_reg.sync_0_LP_and_PED_freq;
258 v_reg.sync_1_LP1_LP2_PED_ratio := i_reg.sync_0_LP1_LP2_PED_ratio;
259 v_reg.sync_1_maj_coinc_n_phys := i_reg.sync_0_maj_coinc_n_phys;
260 v_reg.sync_1_maj_coinc_n_calib := i_reg.sync_0_maj_coinc_n_calib;
261 v_reg.sync_1_trigger_delay := i_reg.sync_0_trigger_delay;
262 v_reg.sync_1_TIM_delay := i_reg.sync_0_TIM_delay;
263 v_reg.sync_1_dead_time := i_reg.sync_0_dead_time;
264 v_reg.sync_1_coinc_window_phys := i_reg.sync_0_coinc_window_phys;
265 v_reg.sync_1_coinc_window_calib := i_reg.sync_0_coinc_window_calib;
266 v_reg.sync_1_active_FTU_list_0 := i_reg.sync_0_active_FTU_list_0;
267 v_reg.sync_1_active_FTU_list_1 := i_reg.sync_0_active_FTU_list_1;
268 v_reg.sync_1_active_FTU_list_2 := i_reg.sync_0_active_FTU_list_2;
269 v_reg.sync_1_active_FTU_list_3 := i_reg.sync_0_active_FTU_list_3;
270 --===================================================================================
271
272 --===================================================================================
273 -- Drive register input
274 i_next_reg <= v_reg;
275
276 --===================================================================================
277 -- Output assignation
278 config_done <= i_reg.config_done(1);
279 sync_start_run <= i_reg.sync_1_start_run;
280 sync_stop_run <= i_reg.sync_1_stop_run;
281 sync_general_settings <= i_reg.sync_1_general_settings;
282 sync_LP_and_PED_freq <= i_reg.sync_1_LP_and_PED_freq;
283 sync_LP1_LP2_PED_ratio <= i_reg.sync_1_LP1_LP2_PED_ratio;
284 sync_maj_coinc_n_phys <= i_reg.sync_1_maj_coinc_n_phys;
285 sync_maj_coinc_n_calib <= i_reg.sync_1_maj_coinc_n_calib;
286 sync_trigger_delay <= i_reg.sync_1_trigger_delay;
287 sync_TIM_delay <= i_reg.sync_1_TIM_delay;
288 sync_dead_time <= i_reg.sync_1_dead_time;
289 sync_coinc_window_phys <= i_reg.sync_1_coinc_window_phys;
290 sync_coinc_window_calib <= i_reg.sync_1_coinc_window_calib;
291 sync_active_FTU_list_0 <= i_reg.sync_1_active_FTU_list_0;
292 sync_active_FTU_list_1 <= i_reg.sync_1_active_FTU_list_1;
293 sync_active_FTU_list_2 <= i_reg.sync_1_active_FTU_list_2;
294 sync_active_FTU_list_3 <= i_reg.sync_1_active_FTU_list_3;
295 --===================================================================================
296 end process;
297
298 -- Sequential logic
299 process(clk_250MHz)
300 begin
301 if rising_edge(clk_250MHz) then
302 i_reg <= i_next_reg;
303 end if;
304 end process;
305
306end RTL;
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