| 1 | --=======================================================================================
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| 2 | -- TITLE : Interface synchronization to 250MHz
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| 3 | -- DESCRIPTION : Synchronize incoming settings to the 250MHz clock
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| 4 | -- FILE : interface_sync_250MHz.vhd
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| 5 | -- COMPANY : Micro-Cameras & Space Exploration SA
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| 6 | --=======================================================================================
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| 7 | -- CREATION
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| 8 | -- DATE AUTHOR PROJECT REVISION
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| 9 | -- 11/03/2011 JGi 110311a
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| 10 | --=======================================================================================
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| 11 | -- MODIFICATION HISTORY
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| 12 | -- DATE AUTHOR PROJECT REVISION COMMENTS
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| 13 | -- 11/03/2011 JGi 110311a Description
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| 14 | --=======================================================================================
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| 15 | -- Library Definition
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| 16 | library ieee;
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| 17 | use ieee.std_logic_1164.all;
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| 18 | use ieee.numeric_std.all;
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| 19 |
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| 20 | -- Entity Definition
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| 21 | entity interface_sync_250MHz is
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| 22 | port( --clock
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| 23 | clk_250MHz : in std_logic;
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| 24 | --inputs
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| 25 | start_run : in std_logic;
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| 26 | stop_run : in std_logic;
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| 27 | new_config : in std_logic;
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| 28 | general_settings : in std_logic_vector(15 downto 0);
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| 29 | LP_and_PED_freq : in std_logic_vector(15 downto 0);
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| 30 | LP1_LP2_PED_ratio : in std_logic_vector(15 downto 0);
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| 31 | maj_coinc_n_phys : in std_logic_vector(15 downto 0);
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| 32 | maj_coinc_n_calib : in std_logic_vector(15 downto 0);
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| 33 | trigger_delay : in std_logic_vector(15 downto 0);
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| 34 | TIM_delay : in std_logic_vector(15 downto 0);
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| 35 | dead_time : in std_logic_vector(15 downto 0);
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| 36 | coinc_window_phys : in std_logic_vector(15 downto 0);
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| 37 | coinc_window_calib : in std_logic_vector(15 downto 0);
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| 38 | active_FTU_list_0 : in std_logic_vector(15 downto 0);
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| 39 | active_FTU_list_1 : in std_logic_vector(15 downto 0);
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| 40 | active_FTU_list_2 : in std_logic_vector(15 downto 0);
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| 41 | active_FTU_list_3 : in std_logic_vector(15 downto 0);
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| 42 | --outputs
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| 43 | config_done : out std_logic;
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| 44 | sync_start_run : out std_logic;
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| 45 | sync_stop_run : out std_logic;
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| 46 | sync_general_settings : out std_logic_vector(7 downto 0);
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| 47 | sync_LP_and_PED_freq : out std_logic_vector(9 downto 0);
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| 48 | sync_LP1_LP2_PED_ratio : out std_logic_vector(14 downto 0);
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| 49 | sync_maj_coinc_n_phys : out std_logic_vector(5 downto 0);
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| 50 | sync_maj_coinc_n_calib : out std_logic_vector(5 downto 0);
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| 51 | sync_trigger_delay : out std_logic_vector(9 downto 0);
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| 52 | sync_TIM_delay : out std_logic_vector(9 downto 0);
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| 53 | sync_dead_time : out std_logic_vector(15 downto 0);
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| 54 | sync_coinc_window_phys : out std_logic_vector(3 downto 0);
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| 55 | sync_coinc_window_calib : out std_logic_vector(3 downto 0);
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| 56 | sync_active_FTU_list_0 : out std_logic_vector(9 downto 0);
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| 57 | sync_active_FTU_list_1 : out std_logic_vector(9 downto 0);
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| 58 | sync_active_FTU_list_2 : out std_logic_vector(9 downto 0);
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| 59 | sync_active_FTU_list_3 : out std_logic_vector(9 downto 0));
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| 60 | end interface_sync_250MHz;
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| 61 |
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| 62 | -- Architecture Definition
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| 63 | architecture RTL of interface_sync_250MHz is
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| 64 |
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| 65 | type t_reg is record
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| 66 | -- Internal register declaration
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| 67 | -- Ouput register declaration
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| 68 | config_done : std_logic_vector(1 downto 0);
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| 69 | sync_0_start_run : std_logic;
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| 70 | sync_1_start_run : std_logic;
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| 71 | sync_0_stop_run : std_logic;
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| 72 | sync_1_stop_run : std_logic;
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| 73 | sync_0_new_config : std_logic;
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| 74 | sync_1_new_config : std_logic;
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| 75 | sync_0_general_settings : std_logic_vector(7 downto 0);
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| 76 | sync_1_general_settings : std_logic_vector(7 downto 0);
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| 77 | sync_0_LP_and_PED_freq : std_logic_vector(9 downto 0);
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| 78 | sync_1_LP_and_PED_freq : std_logic_vector(9 downto 0);
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| 79 | sync_0_LP1_LP2_PED_ratio : std_logic_vector(14 downto 0);
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| 80 | sync_1_LP1_LP2_PED_ratio : std_logic_vector(14 downto 0);
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| 81 | sync_0_maj_coinc_n_phys : std_logic_vector(5 downto 0);
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| 82 | sync_1_maj_coinc_n_phys : std_logic_vector(5 downto 0);
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| 83 | sync_0_maj_coinc_n_calib : std_logic_vector(5 downto 0);
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| 84 | sync_1_maj_coinc_n_calib : std_logic_vector(5 downto 0);
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| 85 | sync_0_trigger_delay : std_logic_vector(9 downto 0);
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| 86 | sync_1_trigger_delay : std_logic_vector(9 downto 0);
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| 87 | sync_0_TIM_delay : std_logic_vector(9 downto 0);
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| 88 | sync_1_TIM_delay : std_logic_vector(9 downto 0);
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| 89 | sync_0_dead_time : std_logic_vector(15 downto 0);
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| 90 | sync_1_dead_time : std_logic_vector(15 downto 0);
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| 91 | sync_0_coinc_window_phys : std_logic_vector(3 downto 0);
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| 92 | sync_1_coinc_window_phys : std_logic_vector(3 downto 0);
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| 93 | sync_0_coinc_window_calib : std_logic_vector(3 downto 0);
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| 94 | sync_1_coinc_window_calib : std_logic_vector(3 downto 0);
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| 95 | sync_0_active_FTU_list_0 : std_logic_vector(9 downto 0);
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| 96 | sync_1_active_FTU_list_0 : std_logic_vector(9 downto 0);
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| 97 | sync_0_active_FTU_list_1 : std_logic_vector(9 downto 0);
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| 98 | sync_1_active_FTU_list_1 : std_logic_vector(9 downto 0);
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| 99 | sync_0_active_FTU_list_2 : std_logic_vector(9 downto 0);
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| 100 | sync_1_active_FTU_list_2 : std_logic_vector(9 downto 0);
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| 101 | sync_0_active_FTU_list_3 : std_logic_vector(9 downto 0);
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| 102 | sync_1_active_FTU_list_3 : std_logic_vector(9 downto 0);
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| 103 | end record;
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| 104 |
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| 105 | signal i_next_reg : t_reg := (config_done => (others => '0'),
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| 106 | sync_0_start_run => '0',
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| 107 | sync_1_start_run => '0',
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| 108 | sync_0_stop_run => '0',
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| 109 | sync_1_stop_run => '0',
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| 110 | sync_0_new_config => '0',
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| 111 | sync_1_new_config => '0',
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| 112 | sync_0_general_settings => (others => '0'),
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| 113 | sync_1_general_settings => (others => '0'),
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| 114 | sync_0_LP_and_PED_freq => (others => '0'),
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| 115 | sync_1_LP_and_PED_freq => (others => '0'),
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| 116 | sync_0_LP1_LP2_PED_ratio => (others => '0'),
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| 117 | sync_1_LP1_LP2_PED_ratio => (others => '0'),
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| 118 | sync_0_maj_coinc_n_phys => (others => '1'),
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| 119 | sync_1_maj_coinc_n_phys => (others => '1'),
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| 120 | sync_0_maj_coinc_n_calib => (others => '1'),
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| 121 | sync_1_maj_coinc_n_calib => (others => '1'),
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| 122 | sync_0_trigger_delay => (others => '0'),
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| 123 | sync_1_trigger_delay => (others => '0'),
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| 124 | sync_0_TIM_delay => (others => '0'),
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| 125 | sync_1_TIM_delay => (others => '0'),
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| 126 | sync_0_dead_time => (others => '0'),
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| 127 | sync_1_dead_time => (others => '0'),
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| 128 | sync_0_coinc_window_phys => (others => '0'),
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| 129 | sync_1_coinc_window_phys => (others => '0'),
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| 130 | sync_0_coinc_window_calib => (others => '0'),
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| 131 | sync_1_coinc_window_calib => (others => '0'),
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| 132 | sync_0_active_FTU_list_0 => (others => '0'),
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| 133 | sync_1_active_FTU_list_0 => (others => '0'),
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| 134 | sync_0_active_FTU_list_1 => (others => '0'),
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| 135 | sync_1_active_FTU_list_1 => (others => '0'),
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| 136 | sync_0_active_FTU_list_2 => (others => '0'),
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| 137 | sync_1_active_FTU_list_2 => (others => '0'),
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| 138 | sync_0_active_FTU_list_3 => (others => '0'),
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| 139 | sync_1_active_FTU_list_3 => (others => '0'));
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| 140 | signal i_reg : t_reg := (config_done => (others => '0'),
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| 141 | sync_0_start_run => '0',
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| 142 | sync_1_start_run => '0',
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| 143 | sync_0_stop_run => '0',
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| 144 | sync_1_stop_run => '0',
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| 145 | sync_0_new_config => '0',
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| 146 | sync_1_new_config => '0',
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| 147 | sync_0_general_settings => (others => '0'),
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| 148 | sync_1_general_settings => (others => '0'),
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| 149 | sync_0_LP_and_PED_freq => (others => '0'),
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| 150 | sync_1_LP_and_PED_freq => (others => '0'),
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| 151 | sync_0_LP1_LP2_PED_ratio => (others => '0'),
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| 152 | sync_1_LP1_LP2_PED_ratio => (others => '0'),
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| 153 | sync_0_maj_coinc_n_phys => (others => '1'),
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| 154 | sync_1_maj_coinc_n_phys => (others => '1'),
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| 155 | sync_0_maj_coinc_n_calib => (others => '1'),
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| 156 | sync_1_maj_coinc_n_calib => (others => '1'),
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| 157 | sync_0_trigger_delay => (others => '0'),
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| 158 | sync_1_trigger_delay => (others => '0'),
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| 159 | sync_0_TIM_delay => (others => '0'),
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| 160 | sync_1_TIM_delay => (others => '0'),
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| 161 | sync_0_dead_time => (others => '0'),
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| 162 | sync_1_dead_time => (others => '0'),
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| 163 | sync_0_coinc_window_phys => (others => '0'),
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| 164 | sync_1_coinc_window_phys => (others => '0'),
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| 165 | sync_0_coinc_window_calib => (others => '0'),
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| 166 | sync_1_coinc_window_calib => (others => '0'),
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| 167 | sync_0_active_FTU_list_0 => (others => '0'),
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| 168 | sync_1_active_FTU_list_0 => (others => '0'),
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| 169 | sync_0_active_FTU_list_1 => (others => '0'),
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| 170 | sync_1_active_FTU_list_1 => (others => '0'),
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| 171 | sync_0_active_FTU_list_2 => (others => '0'),
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| 172 | sync_1_active_FTU_list_2 => (others => '0'),
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| 173 | sync_0_active_FTU_list_3 => (others => '0'),
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| 174 | sync_1_active_FTU_list_3 => (others => '0'));
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| 175 |
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| 176 | begin
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| 177 |
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| 178 | -- Component instantiation
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| 179 |
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| 180 | -- Combinatorial logic
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| 181 | process(start_run, stop_run, new_config, general_settings, LP_and_PED_freq,
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| 182 | LP1_LP2_PED_ratio, maj_coinc_n_phys, maj_coinc_n_calib, trigger_delay,
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| 183 | TIM_delay, dead_time, coinc_window_phys, coinc_window_calib, active_FTU_list_0,
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| 184 | active_FTU_list_1, active_FTU_list_2, active_FTU_list_3, i_reg)
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| 185 | variable v_reg : t_reg := (config_done => (others => '0'),
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| 186 | sync_0_start_run => '0',
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| 187 | sync_1_start_run => '0',
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| 188 | sync_0_stop_run => '0',
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| 189 | sync_1_stop_run => '0',
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| 190 | sync_0_new_config => '0',
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| 191 | sync_1_new_config => '0',
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| 192 | sync_0_general_settings => (others => '0'),
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| 193 | sync_1_general_settings => (others => '0'),
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| 194 | sync_0_LP_and_PED_freq => (others => '0'),
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| 195 | sync_1_LP_and_PED_freq => (others => '0'),
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| 196 | sync_0_LP1_LP2_PED_ratio => (others => '0'),
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| 197 | sync_1_LP1_LP2_PED_ratio => (others => '0'),
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| 198 | sync_0_maj_coinc_n_phys => (others => '1'),
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| 199 | sync_1_maj_coinc_n_phys => (others => '1'),
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| 200 | sync_0_maj_coinc_n_calib => (others => '1'),
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| 201 | sync_1_maj_coinc_n_calib => (others => '1'),
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| 202 | sync_0_trigger_delay => (others => '0'),
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| 203 | sync_1_trigger_delay => (others => '0'),
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| 204 | sync_0_TIM_delay => (others => '0'),
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| 205 | sync_1_TIM_delay => (others => '0'),
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| 206 | sync_0_dead_time => (others => '0'),
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| 207 | sync_1_dead_time => (others => '0'),
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| 208 | sync_0_coinc_window_phys => (others => '0'),
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| 209 | sync_1_coinc_window_phys => (others => '0'),
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| 210 | sync_0_coinc_window_calib => (others => '0'),
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| 211 | sync_1_coinc_window_calib => (others => '0'),
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| 212 | sync_0_active_FTU_list_0 => (others => '0'),
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| 213 | sync_1_active_FTU_list_0 => (others => '0'),
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| 214 | sync_0_active_FTU_list_1 => (others => '0'),
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| 215 | sync_1_active_FTU_list_1 => (others => '0'),
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| 216 | sync_0_active_FTU_list_2 => (others => '0'),
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| 217 | sync_1_active_FTU_list_2 => (others => '0'),
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| 218 | sync_0_active_FTU_list_3 => (others => '0'),
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| 219 | sync_1_active_FTU_list_3 => (others => '0'));
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| 220 | begin
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| 221 | v_reg := i_reg;
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| 222 | --===================================================================================
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| 223 |
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| 224 | --===================================================================================
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| 225 | -- Double synchronization of incoming signals
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| 226 | --===================================================================================
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| 227 | -- Double synchonize command signals
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| 228 | v_reg.sync_0_start_run := start_run;
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| 229 | v_reg.sync_1_start_run := i_reg.sync_0_start_run;
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| 230 | v_reg.sync_0_stop_run := stop_run;
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| 231 | v_reg.sync_1_stop_run := i_reg.sync_0_stop_run;
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| 232 | v_reg.sync_0_new_config := new_config;
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| 233 | v_reg.sync_1_new_config := i_reg.sync_0_new_config;
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| 234 |
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| 235 | v_reg.config_done(0) := '0';
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| 236 | v_reg.config_done(1) := i_reg.config_done(0);
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| 237 |
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| 238 | -- If new configuration is received, register settings
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| 239 | if i_reg.sync_1_new_config = '1' then
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| 240 | v_reg.config_done(0) := '1';
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| 241 | v_reg.sync_0_general_settings := general_settings(7 downto 0);
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| 242 | v_reg.sync_0_LP_and_PED_freq := LP_and_PED_freq(9 downto 0);
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| 243 | v_reg.sync_0_LP1_LP2_PED_ratio := LP1_LP2_PED_ratio(14 downto 0);
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| 244 | v_reg.sync_0_maj_coinc_n_phys := maj_coinc_n_phys(5 downto 0);
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| 245 | v_reg.sync_0_maj_coinc_n_calib := maj_coinc_n_calib(5 downto 0);
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| 246 | v_reg.sync_0_trigger_delay := trigger_delay(9 downto 0);
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| 247 | v_reg.sync_0_TIM_delay := TIM_delay(9 downto 0);
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| 248 | v_reg.sync_0_dead_time := dead_time(15 downto 0);
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| 249 | v_reg.sync_0_coinc_window_phys := coinc_window_phys(3 downto 0);
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| 250 | v_reg.sync_0_coinc_window_calib := coinc_window_calib(3 downto 0);
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| 251 | v_reg.sync_0_active_FTU_list_0 := active_FTU_list_0(9 downto 0);
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| 252 | v_reg.sync_0_active_FTU_list_1 := active_FTU_list_1(9 downto 0);
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| 253 | v_reg.sync_0_active_FTU_list_2 := active_FTU_list_2(9 downto 0);
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| 254 | v_reg.sync_0_active_FTU_list_3 := active_FTU_list_3(9 downto 0);
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| 255 | end if;
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| 256 | v_reg.sync_1_general_settings := i_reg.sync_0_general_settings;
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| 257 | v_reg.sync_1_LP_and_PED_freq := i_reg.sync_0_LP_and_PED_freq;
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| 258 | v_reg.sync_1_LP1_LP2_PED_ratio := i_reg.sync_0_LP1_LP2_PED_ratio;
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| 259 | v_reg.sync_1_maj_coinc_n_phys := i_reg.sync_0_maj_coinc_n_phys;
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| 260 | v_reg.sync_1_maj_coinc_n_calib := i_reg.sync_0_maj_coinc_n_calib;
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| 261 | v_reg.sync_1_trigger_delay := i_reg.sync_0_trigger_delay;
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| 262 | v_reg.sync_1_TIM_delay := i_reg.sync_0_TIM_delay;
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| 263 | v_reg.sync_1_dead_time := i_reg.sync_0_dead_time;
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| 264 | v_reg.sync_1_coinc_window_phys := i_reg.sync_0_coinc_window_phys;
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| 265 | v_reg.sync_1_coinc_window_calib := i_reg.sync_0_coinc_window_calib;
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| 266 | v_reg.sync_1_active_FTU_list_0 := i_reg.sync_0_active_FTU_list_0;
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| 267 | v_reg.sync_1_active_FTU_list_1 := i_reg.sync_0_active_FTU_list_1;
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| 268 | v_reg.sync_1_active_FTU_list_2 := i_reg.sync_0_active_FTU_list_2;
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| 269 | v_reg.sync_1_active_FTU_list_3 := i_reg.sync_0_active_FTU_list_3;
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| 270 | --===================================================================================
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| 271 |
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| 272 | --===================================================================================
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| 273 | -- Drive register input
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| 274 | i_next_reg <= v_reg;
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| 275 |
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| 276 | --===================================================================================
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| 277 | -- Output assignation
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| 278 | config_done <= i_reg.config_done(1);
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| 279 | sync_start_run <= i_reg.sync_1_start_run;
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| 280 | sync_stop_run <= i_reg.sync_1_stop_run;
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| 281 | sync_general_settings <= i_reg.sync_1_general_settings;
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| 282 | sync_LP_and_PED_freq <= i_reg.sync_1_LP_and_PED_freq;
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| 283 | sync_LP1_LP2_PED_ratio <= i_reg.sync_1_LP1_LP2_PED_ratio;
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| 284 | sync_maj_coinc_n_phys <= i_reg.sync_1_maj_coinc_n_phys;
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| 285 | sync_maj_coinc_n_calib <= i_reg.sync_1_maj_coinc_n_calib;
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| 286 | sync_trigger_delay <= i_reg.sync_1_trigger_delay;
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| 287 | sync_TIM_delay <= i_reg.sync_1_TIM_delay;
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| 288 | sync_dead_time <= i_reg.sync_1_dead_time;
|
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| 289 | sync_coinc_window_phys <= i_reg.sync_1_coinc_window_phys;
|
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| 290 | sync_coinc_window_calib <= i_reg.sync_1_coinc_window_calib;
|
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| 291 | sync_active_FTU_list_0 <= i_reg.sync_1_active_FTU_list_0;
|
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| 292 | sync_active_FTU_list_1 <= i_reg.sync_1_active_FTU_list_1;
|
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| 293 | sync_active_FTU_list_2 <= i_reg.sync_1_active_FTU_list_2;
|
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| 294 | sync_active_FTU_list_3 <= i_reg.sync_1_active_FTU_list_3;
|
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| 295 | --===================================================================================
|
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| 296 | end process;
|
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| 297 |
|
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| 298 | -- Sequential logic
|
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| 299 | process(clk_250MHz)
|
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| 300 | begin
|
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| 301 | if rising_edge(clk_250MHz) then
|
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| 302 | i_reg <= i_next_reg;
|
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| 303 | end if;
|
|---|
| 304 | end process;
|
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| 305 |
|
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| 306 | end RTL; |
|---|
