source: firmware/FTM/trigger/drivers/time_window/time_window.vhd@ 10366

Last change on this file since 10366 was 10366, checked in by weitzel, 10 years ago
FTM trigger manager from MCSE added; DCM arrangement changed; changes in FTM ethernet module
File size: 4.0 KB
Line 
1--=======================================================================================
2-- TITLE : Time window
3-- DESCRIPTION : Time window generation for trigger detection
4-- FILE : time_window.vhd
5-- COMPANY : Micro-Cameras & Space Exploration SA
6--=======================================================================================
7-- CREATION
8-- DATE AUTHOR PROJECT REVISION
9-- 02/03/2011 JGi FTM 110302a
10--=======================================================================================
11-- MODIFICATION HISTORY
12-- DATE AUTHOR PROJECT REVISION COMMENTS
13-- 02/03/2011 JGi FTM 110302a Description
14--=======================================================================================
15-- Library Definition
16library ieee;
17 use ieee.std_logic_1164.all;
18 use ieee.numeric_std.all;
19
20-- Entity Definition
21entity time_window is
22 port( --clock
23 clk_250MHz : in std_logic;
24 --control signal
25 coinc_window : in std_logic_vector(3 downto 0);
26 active_FTU_list_0 : in std_logic_vector(9 downto 0);
27 active_FTU_list_1 : in std_logic_vector(9 downto 0);
28 active_FTU_list_2 : in std_logic_vector(9 downto 0);
29 active_FTU_list_3 : in std_logic_vector(9 downto 0);
30 --trigger detection pulses
31 trig_synch_0_rise : in std_logic_vector(9 downto 0); --crate 0
32 trig_synch_1_rise : in std_logic_vector(9 downto 0); --crate 1
33 trig_synch_2_rise : in std_logic_vector(9 downto 0); --crate 2
34 trig_synch_3_rise : in std_logic_vector(9 downto 0); --crate 3
35 trig_synch_0_fall : in std_logic_vector(9 downto 0); --crate 0
36 trig_synch_1_fall : in std_logic_vector(9 downto 0); --crate 1
37 trig_synch_2_fall : in std_logic_vector(9 downto 0); --crate 2
38 trig_synch_3_fall : in std_logic_vector(9 downto 0); --crate 3
39 --programmed width pulses
40 trig_window_0 : out std_logic_vector(9 downto 0); --crate 0
41 trig_window_1 : out std_logic_vector(9 downto 0); --crate 1
42 trig_window_2 : out std_logic_vector(9 downto 0); --crate 2
43 trig_window_3 : out std_logic_vector(9 downto 0)); --crate 3
44end time_window;
45
46-- Architecture Definition
47architecture RTL of time_window is
48
49 component time_counter is
50 port( clk_250MHz : in std_logic;
51 enable : in std_logic;
52 window : in std_logic_vector(3 downto 0);
53 start_rise : in std_logic;
54 start_fall : in std_logic;
55 counting : out std_logic);
56 end component;
57
58begin
59
60 -- Component instantiation
61 ftu_list_0: for i in 0 to 9 generate
62 time_counter_inst_0: time_counter
63 port map( clk_250MHz => clk_250MHz,
64 enable => active_FTU_list_0(i),
65 window => coinc_window,
66 start_rise => trig_synch_0_rise(i),
67 start_fall => trig_synch_0_fall(i),
68 counting => trig_window_0(i));
69 end generate ftu_list_0;
70
71 ftu_list_1: for i in 0 to 9 generate
72 time_counter_inst_1: time_counter
73 port map( clk_250MHz => clk_250MHz,
74 enable => active_FTU_list_1(i),
75 window => coinc_window,
76 start_rise => trig_synch_1_rise(i),
77 start_fall => trig_synch_1_fall(i),
78 counting => trig_window_1(i));
79 end generate ftu_list_1;
80
81 ftu_list_2: for i in 0 to 9 generate
82 time_counter_inst_2: time_counter
83 port map( clk_250MHz => clk_250MHz,
84 enable => active_FTU_list_2(i),
85 window => coinc_window,
86 start_rise => trig_synch_2_rise(i),
87 start_fall => trig_synch_2_fall(i),
88 counting => trig_window_2(i));
89 end generate ftu_list_2;
90
91 ftu_list_3: for i in 0 to 9 generate
92 time_counter_inst_3: time_counter
93 port map( clk_250MHz => clk_250MHz,
94 enable => active_FTU_list_3(i),
95 window => coinc_window,
96 start_rise => trig_synch_3_rise(i),
97 start_fall => trig_synch_3_fall(i),
98 counting => trig_window_3(i));
99 end generate ftu_list_3;
100
101end RTL;
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