source: firmware/FTM/trigger/drivers/trigger_count_ID/trigger_ID_count.vhd@ 10366

Last change on this file since 10366 was 10366, checked in by weitzel, 10 years ago
FTM trigger manager from MCSE added; DCM arrangement changed; changes in FTM ethernet module
File size: 12.7 KB
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1--=======================================================================================
2-- TITLE : Trigger ID generator
3-- DESCRIPTION : Generates ID each time a counter happen and increment counter
4-- FILE : trigger_ID_count.vhd
5-- COMPANY : Micro-Cameras & Space Exploration SA
6--=======================================================================================
7-- CREATION
8-- DATE AUTHOR PROJECT REVISION
9-- 23/03/2011 JGi 110323a
10--=======================================================================================
11-- MODIFICATION HISTORY
12-- DATE AUTHOR PROJECT REVISION COMMENTS
13-- 23/03/2011 JGi 110323a Description
14--=======================================================================================
15-- Library Definition
16library ieee;
17 use ieee.std_logic_1164.all;
18 use ieee.numeric_std.all;
19
20-- Entity Definition
21entity trigger_ID_count is
22 port( --clock
23 clk_250MHz : in std_logic;
24 --control
25 start_run : in std_logic;
26 stop_run : in std_logic;
27 maj_coinc_n_phys : in std_logic_vector(5 downto 0);
28 maj_coinc_n_calib : in std_logic_vector(5 downto 0);
29 --triggers
30 trigger : in std_logic_vector(8 downto 0);
31 phys_trigger : in std_logic;
32 calib_trigger : in std_logic;
33 internal_trigger : in std_logic_vector(1 downto 0);
34 external_trigger : in std_logic_vector(1 downto 0);
35 --outputs
36 trigger_ID_done : out std_logic;
37 trigger_ID : out std_logic_vector(55 downto 0));
38end trigger_ID_count;
39
40-- Architecture Definition
41architecture RTL of trigger_ID_count is
42
43 type t_reg is record
44 -- Internal register declaration
45 start_run : std_logic;
46 stop_run : std_logic;
47 reset_counter : std_logic;
48 counter : std_logic_vector(31 downto 0);
49 counter_0_done : std_logic;
50 counter_1_done : std_logic_vector(1 downto 0);
51 counter_2_done : std_logic_vector(1 downto 0);
52 counter_3_done : std_logic_vector(1 downto 0);
53 counter_4_done : std_logic_vector(2 downto 0);
54 counter_5_done : std_logic_vector(2 downto 0);
55 counter_6_done : std_logic_vector(2 downto 0);
56 triggers_delay : std_logic_vector(5 downto 0);
57 trigger_type_1 : std_logic_vector(7 downto 0);
58 trigger_type_2 : std_logic_vector(7 downto 0);
59 -- Ouput register declaration
60 trigger_ID_done : std_logic_vector(1 downto 0);
61 trigger_ID : std_logic_vector(55 downto 0);
62 end record;
63
64 signal i_next_reg : t_reg := (start_run => '0',
65 stop_run => '0',
66 reset_counter => '0',
67 counter => (others => '0'),
68 counter_0_done => '0',
69 counter_1_done => (others => '0'),
70 counter_2_done => (others => '0'),
71 counter_3_done => (others => '0'),
72 counter_4_done => (others => '0'),
73 counter_5_done => (others => '0'),
74 counter_6_done => (others => '0'),
75 triggers_delay => (others => '0'),
76 trigger_type_1 => (others => '0'),
77 trigger_type_2 => (others => '0'),
78 trigger_ID_done => (others => '0'),
79 trigger_ID => (others => '0'));
80 signal i_reg : t_reg := (start_run => '0',
81 stop_run => '0',
82 reset_counter => '0',
83 counter => (others => '0'),
84 counter_0_done => '0',
85 counter_1_done => (others => '0'),
86 counter_2_done => (others => '0'),
87 counter_3_done => (others => '0'),
88 counter_4_done => (others => '0'),
89 counter_5_done => (others => '0'),
90 counter_6_done => (others => '0'),
91 triggers_delay => (others => '0'),
92 trigger_type_1 => (others => '0'),
93 trigger_type_2 => (others => '0'),
94 trigger_ID_done => (others => '0'),
95 trigger_ID => (others => '0'));
96
97begin
98
99 -- Component instantiation
100
101 -- Combinatorial logic
102 process(start_run, stop_run, trigger, phys_trigger, calib_trigger, internal_trigger,
103 external_trigger, maj_coinc_n_phys, maj_coinc_n_calib, i_reg)
104 variable v_reg : t_reg := (start_run => '0',
105 stop_run => '0',
106 reset_counter => '0',
107 counter => (others => '0'),
108 counter_0_done => '0',
109 counter_1_done => (others => '0'),
110 counter_2_done => (others => '0'),
111 counter_3_done => (others => '0'),
112 counter_4_done => (others => '0'),
113 counter_5_done => (others => '0'),
114 counter_6_done => (others => '0'),
115 triggers_delay => (others => '0'),
116 trigger_type_1 => (others => '0'),
117 trigger_type_2 => (others => '0'),
118 trigger_ID_done => (others => '0'),
119 trigger_ID => (others => '0'));
120 begin
121 v_reg := i_reg;
122 --===================================================================================
123
124 --===================================================================================
125 -- Trigger counter management
126 --===================================================================================
127 -- Register inputs
128 v_reg.start_run := start_run;
129 v_reg.stop_run := stop_run;
130 -- Reset counter when run is started or stopped
131 v_reg.reset_counter := (start_run and not(i_reg.start_run)) or
132 (stop_run and not(i_reg.stop_run));
133 -- Reset counter when starting or stopping run
134 if i_reg.reset_counter = '1' then
135 v_reg.counter := (others => '0');
136 -- Count when trigger is activated
137 -- 32-bits Counter is splitted on 8 4-bits counter with enables
138 else
139 if trigger(0) = '1' then
140 v_reg.counter(3 downto 0) := std_logic_vector(unsigned(i_reg.counter(3 downto 0))+1);
141 end if;
142 if trigger(1) = '1' then
143 if i_reg.counter_0_done = '1' then
144 v_reg.counter(7 downto 4) := std_logic_vector(unsigned(i_reg.counter(7 downto 4))+1);
145 end if;
146 end if;
147 if trigger(2) = '1' then
148 if i_reg.counter_1_done(1) = '1' then
149 v_reg.counter(11 downto 8) := std_logic_vector(unsigned(i_reg.counter(11 downto 8))+1);
150 end if;
151 end if;
152 if trigger(3) = '1' then
153 if i_reg.counter_2_done(1) = '1' then
154 v_reg.counter(15 downto 12) := std_logic_vector(unsigned(i_reg.counter(15 downto 12))+1);
155 end if;
156 end if;
157 if trigger(4) = '1' then
158 if i_reg.counter_3_done(1) = '1' then
159 v_reg.counter(19 downto 16) := std_logic_vector(unsigned(i_reg.counter(19 downto 16))+1);
160 end if;
161 end if;
162 if trigger(5) = '1' then
163 if i_reg.counter_4_done(2) = '1' then
164 v_reg.counter(23 downto 20) := std_logic_vector(unsigned(i_reg.counter(23 downto 20))+1);
165 end if;
166 end if;
167 if trigger(6) = '1' then
168 if i_reg.counter_5_done(2) = '1' then
169 v_reg.counter(27 downto 24) := std_logic_vector(unsigned(i_reg.counter(27 downto 24))+1);
170 end if;
171 end if;
172 if trigger(7) = '1' then
173 if i_reg.counter_6_done(2) = '1' then
174 v_reg.counter(31 downto 28) := std_logic_vector(unsigned(i_reg.counter(31 downto 28))+1);
175 end if;
176 end if;
177 end if;
178
179 -- Manage splitted counters done signals
180 if i_reg.counter(3 downto 0) = "1111" then
181 v_reg.counter_0_done := '1';
182 else
183 v_reg.counter_0_done := '0';
184 end if;
185 if i_reg.counter(7 downto 4) = "1111" then
186 v_reg.counter_1_done(0) := '1';
187 else
188 v_reg.counter_1_done(0) := '0';
189 end if;
190 if i_reg.counter(11 downto 8) = "1111" then
191 v_reg.counter_2_done(0) := '1';
192 else
193 v_reg.counter_2_done(0) := '0';
194 end if;
195 if i_reg.counter(15 downto 12) = "1111" then
196 v_reg.counter_3_done(0) := '1';
197 else
198 v_reg.counter_3_done(0) := '0';
199 end if;
200 if i_reg.counter(19 downto 16) = "1111" then
201 v_reg.counter_4_done(0) := '1';
202 else
203 v_reg.counter_4_done(0) := '0';
204 end if;
205 if i_reg.counter(23 downto 20) = "1111" then
206 v_reg.counter_5_done(0) := '1';
207 else
208 v_reg.counter_5_done(0) := '0';
209 end if;
210 if i_reg.counter(27 downto 24) = "1111" then
211 v_reg.counter_6_done(0) := '1';
212 else
213 v_reg.counter_6_done(0) := '0';
214 end if;
215
216 -- Enables are splitted to use only 4-bits LUT
217 -- Delay between two trigger is long enough to allow delay on enables
218 v_reg.counter_1_done(1) := i_reg.counter_0_done and i_reg.counter_1_done(0);
219 v_reg.counter_2_done(1) := i_reg.counter_0_done and i_reg.counter_1_done(0) and
220 i_reg.counter_2_done(0);
221 v_reg.counter_3_done(1) := i_reg.counter_0_done and i_reg.counter_1_done(0) and
222 i_reg.counter_2_done(0) and i_reg.counter_3_done(0);
223 v_reg.counter_4_done(1) := i_reg.counter_0_done and i_reg.counter_1_done(0) and
224 i_reg.counter_2_done(0) and i_reg.counter_3_done(0);
225 v_reg.counter_4_done(2) := i_reg.counter_4_done(1) and i_reg.counter_4_done(0);
226 v_reg.counter_5_done(1) := i_reg.counter_0_done and i_reg.counter_1_done(0) and
227 i_reg.counter_2_done(0) and i_reg.counter_3_done(0);
228 v_reg.counter_5_done(2) := i_reg.counter_5_done(1) and i_reg.counter_4_done(0) and
229 i_reg.counter_5_done(0);
230 v_reg.counter_6_done(1) := i_reg.counter_0_done and i_reg.counter_1_done(0) and
231 i_reg.counter_2_done(0) and i_reg.counter_3_done(0);
232 v_reg.counter_6_done(2) := i_reg.counter_6_done(1) and i_reg.counter_4_done(0) and
233 i_reg.counter_5_done(0) and i_reg.counter_6_done(0);
234 --===================================================================================
235
236 --===================================================================================
237 -- Trigger type management
238 --===================================================================================
239 -- Register trigger types inputs
240 v_reg.triggers_delay(0) := phys_trigger;
241 v_reg.triggers_delay(1) := calib_trigger;
242 v_reg.triggers_delay(2) := internal_trigger(0);
243 v_reg.triggers_delay(3) := internal_trigger(1);
244 v_reg.triggers_delay(4) := external_trigger(0);
245 v_reg.triggers_delay(5) := external_trigger(1);
246 v_reg.trigger_ID_done(0) := '0';
247 v_reg.trigger_ID_done(1) := i_reg.trigger_ID_done(0);
248
249 -- If master trigger fires
250 if trigger(8) = '1' then
251 -- Manage trigger ready output
252 v_reg.trigger_ID_done(0) := '1';
253 -- Manage trigger ID content
254 -- If physics event
255 if i_reg.triggers_delay(0) = '1' then
256 v_reg.trigger_type_1(7 downto 2) := maj_coinc_n_phys;
257 -- If calibration events
258 elsif i_reg.triggers_delay(1) = '1' then
259 v_reg.trigger_type_1(7 downto 2) := maj_coinc_n_calib;
260 else
261 v_reg.trigger_type_1(7 downto 2) := (others => '0');
262 end if;
263 v_reg.trigger_type_2(7 downto 3) := (others => '0');
264 -- If not a physics event
265 if i_reg.triggers_delay(0) = '0' then
266 v_reg.trigger_type_1(1 downto 0) := i_reg.triggers_delay(5 downto 4);
267 v_reg.trigger_type_2(2) := i_reg.triggers_delay(3);
268 v_reg.trigger_type_2(1) := i_reg.triggers_delay(2);
269 v_reg.trigger_type_2(0) := i_reg.triggers_delay(1);
270 else
271 v_reg.trigger_type_1(1 downto 0) := (others => '0');
272 v_reg.trigger_type_2(2 downto 0) := (others => '0');
273 end if;
274 end if;
275 --===================================================================================
276
277 --===================================================================================
278 -- Trigger ID management
279 --===================================================================================
280 v_reg.trigger_ID(31 downto 0) := i_reg.counter;
281 v_reg.trigger_ID(39 downto 32) := i_reg.trigger_type_1;
282 v_reg.trigger_ID(47 downto 40) := i_reg.trigger_type_2;
283 v_reg.trigger_ID(55 downto 48) := (others => '0');
284 --===================================================================================
285
286 --===================================================================================
287 -- Drive register input
288 i_next_reg <= v_reg;
289
290 --===================================================================================
291 -- Output assignation
292 trigger_ID_done <= i_reg.trigger_ID_done(1);
293 trigger_ID <= i_reg.trigger_ID;
294 --===================================================================================
295 end process;
296
297 -- Sequential logic
298 process(clk_250MHz)
299 begin
300 if rising_edge(clk_250MHz) then
301 i_reg <= i_next_reg;
302 end if;
303 end process;
304
305end RTL;
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