| 1 | --=======================================================================================
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| 2 | -- TITLE : Pulse generation with programmable delay
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| 3 | -- DESCRIPTION : Generate pulse from an input with a programmable delay and width
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| 4 | -- FILE : time_counter.vhd
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| 5 | -- COMPANY : Micro-Cameras & Space Exploration SA
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| 6 | --=======================================================================================
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| 7 | -- CREATION
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| 8 | -- DATE AUTHOR PROJECT REVISION
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| 9 | -- 02/03/2011 JGi FTM 110302a
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| 10 | --=======================================================================================
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| 11 | -- MODIFICATION HISTORY
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| 12 | -- DATE AUTHOR PROJECT REVISION COMMENTS
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| 13 | -- 02/03/2011 JGi FTM 110302a Description
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| 14 | --=======================================================================================
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| 15 | -- Library Definition
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| 16 | library ieee;
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| 17 | use ieee.std_logic_1164.all;
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| 18 | use ieee.numeric_std.all;
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| 19 |
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| 20 | library unisim;
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| 21 | use unisim.vcomponents.all;
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| 22 |
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| 23 | -- Entity Definition
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| 24 | entity delayed_pulse is
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| 25 | generic( pulse_width : integer range 0 to 15 := 10);
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| 26 | port( --clock
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| 27 | clk_250MHz : in std_logic;
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| 28 | --control
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| 29 | delay : in std_logic_vector(9 downto 0);
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| 30 | --I/O
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| 31 | input : in std_logic;
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| 32 | output : out std_logic);
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| 33 | end delayed_pulse;
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| 34 |
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| 35 | -- Architecture Definition
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| 36 | architecture RTL of delayed_pulse is
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| 37 |
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| 38 | type t_reg is record
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| 39 | -- Internal register declaration
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| 40 | delayed_input : std_logic;
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| 41 | enable : std_logic_vector(3 downto 0);
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| 42 | delay : std_logic_vector(9 downto 0);
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| 43 | delay_counter : std_logic_vector(9 downto 0);
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| 44 | delay_value_reached : std_logic_vector(2 downto 0);
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| 45 | delay_0_done : std_logic_vector(1 downto 0);
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| 46 | delay_1_done : std_logic;
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| 47 | pulse_shifter : std_logic_vector(pulse_width downto 0);
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| 48 | -- Ouput register declaration
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| 49 | output : std_logic_vector(1 downto 0);
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| 50 | end record;
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| 51 |
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| 52 | signal i_next_reg : t_reg := (delayed_input => '0',
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| 53 | enable => (others => '0'),
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| 54 | delay => (others => '0'),
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| 55 | delay_counter => (others => '0'),
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| 56 | delay_value_reached => (others => '0'),
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| 57 | delay_0_done => (others => '0'),
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| 58 | delay_1_done => '0',
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| 59 | pulse_shifter => (others => '0'),
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| 60 | output => (others => '0'));
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| 61 | signal i_reg : t_reg := (delayed_input => '0',
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| 62 | enable => (others => '0'),
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| 63 | delay => (others => '0'),
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| 64 | delay_counter => (others => '0'),
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| 65 | delay_value_reached => (others => '0'),
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| 66 | delay_0_done => (others => '0'),
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| 67 | delay_1_done => '0',
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| 68 | pulse_shifter => (others => '0'),
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| 69 | output => (others => '0'));
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| 70 |
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| 71 | signal i_shifted_data : std_logic;
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| 72 |
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| 73 | begin
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| 74 |
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| 75 | -- Generate shift register depending on pulse width generic
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| 76 | -- defined in ftm_definitions
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| 77 | -- Shifter logic
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| 78 | gen_shifter_0: if pulse_width = 0 generate
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| 79 | process(clk_250MHz)
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| 80 | variable shifter : std_logic := '0';
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| 81 | begin
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| 82 | if rising_edge(clk_250MHz) then
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| 83 | shifter := i_reg.output(0) and not(i_reg.output(1));
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| 84 | end if;
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| 85 | i_shifted_data <= shifter;
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| 86 | end process;
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| 87 | end generate gen_shifter_0;
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| 88 | gen_shifter_1: if pulse_width > 0 generate
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| 89 | process(clk_250MHz)
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| 90 | variable shifter : std_logic_vector(pulse_width downto 0) := (others => '0');
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| 91 | begin
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| 92 | if rising_edge(clk_250MHz) then
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| 93 | shifter := shifter(pulse_width-1 downto 0) & (i_reg.output(0) and not(i_reg.output(1)));
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| 94 | end if;
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| 95 | i_shifted_data <= shifter(pulse_width);
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| 96 | end process;
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| 97 | end generate gen_shifter_1;
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| 98 |
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| 99 | -- Combinatorial logic
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| 100 | process(input, delay, i_shifted_data, i_reg)
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| 101 | variable v_reg : t_reg := (delayed_input => '0',
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| 102 | enable => (others => '0'),
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| 103 | delay => (others => '0'),
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| 104 | delay_counter => (others => '0'),
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| 105 | delay_value_reached => (others => '0'),
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| 106 | delay_0_done => (others => '0'),
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| 107 | delay_1_done => '0',
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| 108 | pulse_shifter => (others => '0'),
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| 109 | output => (others => '0'));
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| 110 | begin
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| 111 | v_reg := i_reg;
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| 112 | --===================================================================================
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| 113 |
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| 114 | --===================================================================================
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| 115 | -- Delay Counter management
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| 116 | --===================================================================================
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| 117 | -- Register delay
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| 118 | v_reg.delay := delay;
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| 119 |
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| 120 | -- Count delay when input (master trigger) rising edge detected
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| 121 | if i_reg.enable(0) = '1' then
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| 122 | v_reg.delay_counter(3 downto 0) := std_logic_vector(unsigned(i_reg.delay_counter(3 downto 0))+1);
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| 123 | if i_reg.delay_0_done(1) = '1' then
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| 124 | v_reg.delay_counter(7 downto 4) := std_logic_vector(unsigned(i_reg.delay_counter(7 downto 4))+1);
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| 125 | end if;
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| 126 | if i_reg.delay_1_done = '1' then
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| 127 | v_reg.delay_counter(9 downto 8) := std_logic_vector(unsigned(i_reg.delay_counter(9 downto 8))+1);
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| 128 | end if;
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| 129 | else
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| 130 | v_reg.delay_counter := (others => '0');
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| 131 | end if;
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| 132 |
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| 133 | v_reg.delayed_input := input;
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| 134 |
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| 135 | -- Detect input (master trigger) rising edge to enable counting
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| 136 | if input = '1' and i_reg.delayed_input = '0' then
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| 137 | v_reg.enable := (others => '1');
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| 138 | end if;
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| 139 |
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| 140 | -- Generate partial comparison between counter and setting
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| 141 | if i_reg.delay_counter(3 downto 0) = i_reg.delay(3 downto 0) then
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| 142 | v_reg.delay_value_reached(0) := i_reg.enable(1);
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| 143 | else
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| 144 | v_reg.delay_value_reached(0) := '0';
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| 145 | end if;
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| 146 | if i_reg.delay_counter(7 downto 4) = i_reg.delay(7 downto 4) then
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| 147 | v_reg.delay_value_reached(1) := i_reg.enable(1);
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| 148 | else
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| 149 | v_reg.delay_value_reached(1) := '0';
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| 150 | end if;
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| 151 | if i_reg.delay_counter(9 downto 8) = i_reg.delay(9 downto 8) then
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| 152 | v_reg.delay_value_reached(2) := i_reg.enable(1);
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| 153 | else
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| 154 | v_reg.delay_value_reached(2) := '0';
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| 155 | end if;
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| 156 |
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| 157 | -- Generate partial counter enable
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| 158 | if i_reg.delay_counter(3 downto 0) = "1101" then
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| 159 | v_reg.delay_0_done(0) := i_reg.enable(2);
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| 160 | else
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| 161 | v_reg.delay_0_done(0) := '0';
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| 162 | end if;
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| 163 | v_reg.delay_0_done(1) := i_reg.delay_0_done(0) and i_reg.enable(2);
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| 164 |
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| 165 | if i_reg.delay_counter(7 downto 4) = "1111" then
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| 166 | v_reg.delay_1_done := i_reg.delay_0_done(0) and i_reg.enable(2);
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| 167 | end if;
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| 168 | --===================================================================================
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| 169 |
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| 170 | --===================================================================================
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| 171 | -- Pulse Counter management
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| 172 | --===================================================================================
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| 173 | -- Enable output when delay is reached, and disable it after shift register
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| 174 | -- has finished
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| 175 | if i_shifted_data = '1' then
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| 176 | v_reg.output(0) := '0';
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| 177 | elsif i_reg.delay_value_reached = "111" and i_reg.enable(3) = '1' then
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| 178 | v_reg.output(0) := '1';
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| 179 | v_reg.pulse_shifter(0) := '1';
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| 180 | end if;
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| 181 |
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| 182 | -- Once the output falls, reset enable
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| 183 | if i_reg.output(1) = '1' and i_reg.output(0) = '0' then
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| 184 | v_reg.enable := (others => '0');
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| 185 | end if;
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| 186 |
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| 187 | v_reg.output(1) := i_reg.output(0);
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| 188 | --===================================================================================
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| 189 |
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| 190 | --===================================================================================
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| 191 | -- Drive register input
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| 192 | i_next_reg <= v_reg;
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| 193 |
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| 194 | --===================================================================================
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| 195 | -- Output assignation
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| 196 | output <= i_reg.output(0);
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| 197 | --===================================================================================
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| 198 | end process;
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| 199 |
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| 200 | -- Sequential logic
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| 201 | process(clk_250MHz)
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| 202 | begin
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| 203 | if rising_edge(clk_250MHz) then
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| 204 | i_reg <= i_next_reg;
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| 205 | end if;
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| 206 | end process;
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| 207 |
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| 208 | end RTL; |
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