source: firmware/FTM/trigger/ftm_trigger/trigger_manager.vhd@ 11787

Last change on this file since 11787 was 10366, checked in by weitzel, 15 years ago
FTM trigger manager from MCSE added; DCM arrangement changed; changes in FTM ethernet module
File size: 16.2 KB
Line 
1--=======================================================================================
2-- TITLE : Trigger manager
3-- DESCRIPTION : Top architecture file to detect events and generate triggers
4-- FILE : trigger_manager.vhd
5-- COMPANY : Micro-Cameras & Space Exploration SA
6--=======================================================================================
7-- CREATION
8-- DATE AUTHOR PROJECT REVISION
9-- 09/03/2011 JGi 110309a
10--=======================================================================================
11-- MODIFICATION HISTORY
12-- DATE AUTHOR PROJECT REVISION COMMENTS
13-- 09/03/2011 JGi 110309a Description
14--=======================================================================================
15-- Library Definition
16library ieee;
17 use ieee.std_logic_1164.all;
18 use ieee.numeric_std.all;
19
20-- Entity Definition
21entity trigger_manager is
22 port( --clocks
23 clk_50MHz : in std_logic;
24 clk_250MHz : in std_logic;
25 clk_250MHz_180 : in std_logic;
26 --trigger primitives from FTUs
27 trig_prim_0 : in std_logic_vector(9 downto 0); --crate 0
28 trig_prim_1 : in std_logic_vector(9 downto 0); --crate 1
29 trig_prim_2 : in std_logic_vector(9 downto 0); --crate 2
30 trig_prim_3 : in std_logic_vector(9 downto 0); --crate 3
31 --external signals
32 ext_trig_1 : in std_logic;
33 ext_trig_2 : in std_logic;
34 ext_veto : in std_logic;
35 FAD_busy_0 : in std_logic; --crate 0
36 FAD_busy_1 : in std_logic; --crate 1
37 FAD_busy_2 : in std_logic; --crate 2
38 FAD_busy_3 : in std_logic; --crate 3
39 --control signals from e.g. main control
40 start_run : in std_logic; --enable trigger output
41 stop_run : in std_logic; --disable trigger output
42 new_config : in std_logic;
43 --settings register (see FTM Firmware Specifications)
44 general_settings : in std_logic_vector(15 downto 0);
45 LP_and_PED_freq : in std_logic_vector(15 downto 0);
46 LP1_LP2_PED_ratio : in std_logic_vector(15 downto 0);
47 maj_coinc_n_phys : in std_logic_vector(15 downto 0);
48 maj_coinc_n_calib : in std_logic_vector(15 downto 0);
49 trigger_delay : in std_logic_vector(15 downto 0);
50 TIM_delay : in std_logic_vector(15 downto 0);
51 dead_time : in std_logic_vector(15 downto 0);
52 coinc_window_phys : in std_logic_vector(15 downto 0);
53 coinc_window_calib : in std_logic_vector(15 downto 0);
54 active_FTU_list_0 : in std_logic_vector(15 downto 0);
55 active_FTU_list_1 : in std_logic_vector(15 downto 0);
56 active_FTU_list_2 : in std_logic_vector(15 downto 0);
57 active_FTU_list_3 : in std_logic_vector(15 downto 0);
58 --control signals or information for other entities
59 trigger_ID_read : in std_logic;
60 trig_cnt_copy_read : in std_logic;
61 trigger_ID_ready : out std_logic;
62 trigger_ID : out std_logic_vector(55 downto 0);
63 trig_cnt_copy : out std_logic_vector(31 downto 0); --counter reading
64 trig_cnt_copy_valid : out std_logic; --trigger counter reading is valid
65 trigger_active : out std_logic; --phys triggers are enabled/active
66 config_done : out std_logic;
67 LP1_pulse : out std_logic; --send start signal to light pulser 1
68 LP2_pulse : out std_logic; --send start signal to light pulser 2
69 --trigger and time marker output signals to FADs
70 trigger_signal : out std_logic;
71 TIM_signal : out std_logic);
72end trigger_manager;
73
74-- Architecture Definition
75architecture RTL of trigger_manager is
76
77 component interface_sync_250MHz is
78 port( clk_250MHz : in std_logic;
79 start_run : in std_logic;
80 stop_run : in std_logic;
81 new_config : in std_logic;
82 general_settings : in std_logic_vector(15 downto 0);
83 LP_and_PED_freq : in std_logic_vector(15 downto 0);
84 LP1_LP2_PED_ratio : in std_logic_vector(15 downto 0);
85 maj_coinc_n_phys : in std_logic_vector(15 downto 0);
86 maj_coinc_n_calib : in std_logic_vector(15 downto 0);
87 trigger_delay : in std_logic_vector(15 downto 0);
88 TIM_delay : in std_logic_vector(15 downto 0);
89 dead_time : in std_logic_vector(15 downto 0);
90 coinc_window_phys : in std_logic_vector(15 downto 0);
91 coinc_window_calib : in std_logic_vector(15 downto 0);
92 active_FTU_list_0 : in std_logic_vector(15 downto 0);
93 active_FTU_list_1 : in std_logic_vector(15 downto 0);
94 active_FTU_list_2 : in std_logic_vector(15 downto 0);
95 active_FTU_list_3 : in std_logic_vector(15 downto 0);
96 config_done : out std_logic;
97 sync_start_run : out std_logic;
98 sync_stop_run : out std_logic;
99 sync_general_settings : out std_logic_vector(7 downto 0);
100 sync_LP_and_PED_freq : out std_logic_vector(9 downto 0);
101 sync_LP1_LP2_PED_ratio : out std_logic_vector(14 downto 0);
102 sync_maj_coinc_n_phys : out std_logic_vector(5 downto 0);
103 sync_maj_coinc_n_calib : out std_logic_vector(5 downto 0);
104 sync_trigger_delay : out std_logic_vector(9 downto 0);
105 sync_TIM_delay : out std_logic_vector(9 downto 0);
106 sync_dead_time : out std_logic_vector(15 downto 0);
107 sync_coinc_window_phys : out std_logic_vector(3 downto 0);
108 sync_coinc_window_calib : out std_logic_vector(3 downto 0);
109 sync_active_FTU_list_0 : out std_logic_vector(9 downto 0);
110 sync_active_FTU_list_1 : out std_logic_vector(9 downto 0);
111 sync_active_FTU_list_2 : out std_logic_vector(9 downto 0);
112 sync_active_FTU_list_3 : out std_logic_vector(9 downto 0));
113 end component;
114
115 signal i_config_done : std_logic := '0';
116 signal i_sync_start_run : std_logic := '0';
117 signal i_sync_stop_run : std_logic := '0';
118 signal i_sync_general_settings : std_logic_vector(7 downto 0) := (others => '0');
119 signal i_sync_LP_and_PED_freq : std_logic_vector(9 downto 0) := (others => '0');
120 signal i_sync_LP1_LP2_PED_ratio : std_logic_vector(14 downto 0) := (others => '0');
121 signal i_sync_maj_coinc_n_phys : std_logic_vector(5 downto 0) := (others => '0');
122 signal i_sync_maj_coinc_n_calib : std_logic_vector(5 downto 0) := (others => '0');
123 signal i_sync_trigger_delay : std_logic_vector(9 downto 0) := (others => '0');
124 signal i_sync_TIM_delay : std_logic_vector(9 downto 0) := (others => '0');
125 signal i_sync_dead_time : std_logic_vector(15 downto 0) := (others => '0');
126 signal i_sync_coinc_window_phys : std_logic_vector(3 downto 0) := (others => '0');
127 signal i_sync_coinc_window_calib : std_logic_vector(3 downto 0) := (others => '0');
128 signal i_sync_active_FTU_list_0 : std_logic_vector(9 downto 0) := (others => '0');
129 signal i_sync_active_FTU_list_1 : std_logic_vector(9 downto 0) := (others => '0');
130 signal i_sync_active_FTU_list_2 : std_logic_vector(9 downto 0) := (others => '0');
131 signal i_sync_active_FTU_list_3 : std_logic_vector(9 downto 0) := (others => '0');
132
133 component interface_sync_50MHz is
134 port( clk_50MHz : in std_logic;
135 clk_250MHz : in std_logic;
136 config_done : in std_logic;
137 trigger_active : in std_logic;
138 trigger_ID_done : in std_logic;
139 trigger_ID : in std_logic_vector(55 downto 0);
140 trigger_ID_read : in std_logic;
141 trigger_cnt_read : in std_logic;
142 sync_config_done : out std_logic;
143 sync_trigger_active : out std_logic;
144 sync_trigger_ID_ready : out std_logic;
145 sync_trigger_ID : out std_logic_vector(55 downto 0);
146 trigger_cnt_valid : out std_logic;
147 trigger_cnt_copy : out std_logic_vector(31 downto 0));
148 end component;
149
150 component FTU_trigger_counter is
151 port( clk_250MHz : in std_logic;
152 clk_250MHz_180 : in std_logic;
153 phys_coinc_window : in std_logic_vector(3 downto 0);
154 calib_coinc_window : in std_logic_vector(3 downto 0);
155 active_FTU_list_0 : in std_logic_vector(9 downto 0);
156 active_FTU_list_1 : in std_logic_vector(9 downto 0);
157 active_FTU_list_2 : in std_logic_vector(9 downto 0);
158 active_FTU_list_3 : in std_logic_vector(9 downto 0);
159 trig_prim_0 : in std_logic_vector(9 downto 0);
160 trig_prim_1 : in std_logic_vector(9 downto 0);
161 trig_prim_2 : in std_logic_vector(9 downto 0);
162 trig_prim_3 : in std_logic_vector(9 downto 0);
163 phys_events : out std_logic_vector(5 downto 0);
164 calib_events : out std_logic_vector(5 downto 0));
165 end component;
166
167 signal i_phys_events : std_logic_vector(5 downto 0) := (others => '0');
168 signal i_calib_events : std_logic_vector(5 downto 0) := (others => '0');
169
170 component calibration_pedestal is
171 port( clk_50MHz : in std_logic;
172 new_config : in std_logic;
173 general_settings : in std_logic_vector(7 downto 0);
174 LP_and_PED_freq : in std_logic_vector(9 downto 0);
175 LP1_LP2_PED_ratio : in std_logic_vector(14 downto 0);
176 LP1_pulse : out std_logic;
177 LP2_pulse : out std_logic;
178 PED_pulse : out std_logic);
179 end component;
180
181 signal i_LP1_pulse : std_logic;
182 signal i_LP2_pulse : std_logic;
183 signal i_PED_pulse : std_logic;
184
185 component trigger_generator is
186 port( clk_250MHz : in std_logic;
187 start_run : in std_logic;
188 stop_run : in std_logic;
189 general_settings : in std_logic_vector(7 downto 0);
190 maj_coinc_n_phys : in std_logic_vector(5 downto 0);
191 maj_coinc_n_calib : in std_logic_vector(5 downto 0);
192 trigger_delay : in std_logic_vector(9 downto 0);
193 TIM_delay : in std_logic_vector(9 downto 0);
194 dead_time : in std_logic_vector(15 downto 0);
195 ext_trig_1 : in std_logic;
196 ext_trig_2 : in std_logic;
197 ext_veto : in std_logic;
198 FAD_busy_0 : in std_logic;
199 FAD_busy_1 : in std_logic;
200 FAD_busy_2 : in std_logic;
201 FAD_busy_3 : in std_logic;
202 phys_events : in std_logic_vector(5 downto 0);
203 calib_events : in std_logic_vector(5 downto 0);
204 LP1_pulse : in std_logic;
205 LP2_pulse : in std_logic;
206 PED_pulse : in std_logic;
207 trigger_ID_done : out std_logic;
208 trigger_ID : out std_logic_vector(55 downto 0);
209 trigger_active : out std_logic;
210 trigger_signal : out std_logic;
211 TIM_signal : out std_logic);
212 end component;
213
214 signal i_trigger_active : std_logic;
215 signal i_trigger_ID_done : std_logic;
216 signal i_trigger_ID : std_logic_vector(55 downto 0);
217
218begin
219
220 -- Component instantiation
221 inst_settings_sync: interface_sync_250MHz
222 port map( clk_250MHz => clk_250MHz,
223 start_run => start_run,
224 stop_run => stop_run,
225 new_config => new_config,
226 general_settings => general_settings,
227 LP_and_PED_freq => LP_and_PED_freq,
228 LP1_LP2_PED_ratio => LP1_LP2_PED_ratio,
229 maj_coinc_n_phys => maj_coinc_n_phys,
230 maj_coinc_n_calib => maj_coinc_n_calib,
231 trigger_delay => trigger_delay,
232 TIM_delay => TIM_delay,
233 dead_time => dead_time,
234 coinc_window_phys => coinc_window_phys,
235 coinc_window_calib => coinc_window_calib,
236 active_FTU_list_0 => active_FTU_list_0,
237 active_FTU_list_1 => active_FTU_list_1,
238 active_FTU_list_2 => active_FTU_list_2,
239 active_FTU_list_3 => active_FTU_list_3,
240 config_done => i_config_done,
241 sync_start_run => i_sync_start_run,
242 sync_stop_run => i_sync_stop_run,
243 sync_general_settings => i_sync_general_settings,
244 sync_LP_and_PED_freq => i_sync_LP_and_PED_freq,
245 sync_LP1_LP2_PED_ratio => i_sync_LP1_LP2_PED_ratio,
246 sync_maj_coinc_n_phys => i_sync_maj_coinc_n_phys,
247 sync_maj_coinc_n_calib => i_sync_maj_coinc_n_calib,
248 sync_trigger_delay => i_sync_trigger_delay,
249 sync_TIM_delay => i_sync_TIM_delay,
250 sync_dead_time => i_sync_dead_time,
251 sync_coinc_window_phys => i_sync_coinc_window_phys,
252 sync_coinc_window_calib => i_sync_coinc_window_calib,
253 sync_active_FTU_list_0 => i_sync_active_FTU_list_0,
254 sync_active_FTU_list_1 => i_sync_active_FTU_list_1,
255 sync_active_FTU_list_2 => i_sync_active_FTU_list_2,
256 sync_active_FTU_list_3 => i_sync_active_FTU_list_3);
257
258 inst_interface_sync: interface_sync_50MHz
259 port map( clk_50MHz => clk_50MHz,
260 clk_250MHz => clk_250MHz,
261 config_done => i_config_done,
262 trigger_active => i_trigger_active,
263 trigger_ID_done => i_trigger_ID_done,
264 trigger_ID => i_trigger_ID,
265 trigger_ID_read => trigger_ID_read,
266 trigger_cnt_read => trig_cnt_copy_read,
267 sync_config_done => config_done,
268 sync_trigger_active => trigger_active,
269 sync_trigger_ID_ready => trigger_ID_ready,
270 sync_trigger_ID => trigger_ID,
271 trigger_cnt_valid => trig_cnt_copy_valid,
272 trigger_cnt_copy => trig_cnt_copy);
273
274 inst_FTU_trig: FTU_trigger_counter
275 port map( clk_250MHz => clk_250MHz,
276 clk_250MHz_180 => clk_250MHz_180,
277 phys_coinc_window => i_sync_coinc_window_phys,
278 calib_coinc_window => i_sync_coinc_window_calib,
279 active_FTU_list_0 => i_sync_active_FTU_list_0,
280 active_FTU_list_1 => i_sync_active_FTU_list_1,
281 active_FTU_list_2 => i_sync_active_FTU_list_2,
282 active_FTU_list_3 => i_sync_active_FTU_list_3,
283 trig_prim_0 => trig_prim_0,
284 trig_prim_1 => trig_prim_1,
285 trig_prim_2 => trig_prim_2,
286 trig_prim_3 => trig_prim_3,
287 phys_events => i_phys_events,
288 calib_events => i_calib_events);
289
290 inst_internal_trig: calibration_pedestal
291 port map( clk_50MHz => clk_50MHz,
292 new_config => new_config,
293 general_settings => general_settings(7 downto 0),
294 LP_and_PED_freq => LP_and_PED_freq(9 downto 0),
295 LP1_LP2_PED_ratio => LP1_LP2_PED_ratio(14 downto 0),
296 LP1_pulse => i_LP1_pulse,
297 LP2_pulse => i_LP2_pulse,
298 PED_pulse => i_PED_pulse);
299
300 inst_trig_gen: trigger_generator
301 port map( clk_250MHz => clk_250MHz,
302 start_run => i_sync_start_run,
303 stop_run => i_sync_stop_run,
304 general_settings => i_sync_general_settings,
305 maj_coinc_n_phys => i_sync_maj_coinc_n_phys,
306 maj_coinc_n_calib => i_sync_maj_coinc_n_calib,
307 trigger_delay => i_sync_trigger_delay,
308 TIM_delay => i_sync_TIM_delay,
309 dead_time => i_sync_dead_time,
310 ext_trig_1 => ext_trig_1,
311 ext_trig_2 => ext_trig_2,
312 ext_veto => ext_veto,
313 FAD_busy_0 => FAD_busy_0,
314 FAD_busy_1 => FAD_busy_1,
315 FAD_busy_2 => FAD_busy_2,
316 FAD_busy_3 => FAD_busy_3,
317 phys_events => i_phys_events,
318 calib_events => i_calib_events,
319 LP1_pulse => i_LP1_pulse,
320 LP2_pulse => i_LP2_pulse,
321 PED_pulse => i_PED_pulse,
322 trigger_ID_done => i_trigger_ID_done,
323 trigger_ID => i_trigger_ID,
324 trigger_active => i_trigger_active,
325 trigger_signal => trigger_signal,
326 TIM_signal => TIM_signal);
327
328 LP1_pulse <= i_LP1_pulse;
329 LP2_pulse <= i_LP2_pulse;
330
331end RTL;
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