source: firmware/FTM/trigger/kernel/trigger_generator/trigger_generator.vhd@ 10366

Last change on this file since 10366 was 10366, checked in by weitzel, 10 years ago
FTM trigger manager from MCSE added; DCM arrangement changed; changes in FTM ethernet module
File size: 17.8 KB
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1--=======================================================================================
2-- TITLE : Trigger generator
3-- DESCRIPTION : Generates triggers from events, calibration pulses or external inputs
4-- FILE : trigger_generator.vhd
5-- COMPANY : Micro-Cameras & Space Exploration SA
6--=======================================================================================
7-- CREATION
8-- DATE AUTHOR PROJECT REVISION
9-- 14/03/2011 JGi 110314a
10--=======================================================================================
11-- MODIFICATION HISTORY
12-- DATE AUTHOR PROJECT REVISION COMMENTS
13-- 14/03/2011 JGi 110314a Description
14-- 13/04/2011 JGi 110413a Update trigger enable management
15--=======================================================================================
16-- Library Definition
17library ieee;
18 use ieee.std_logic_1164.all;
19 use ieee.numeric_std.all;
20
21library ftm_definitions;
22 use ftm_definitions.ftm_array_types.all;
23 use ftm_definitions.ftm_constants.all;
24
25-- Entity Definition
26entity trigger_generator is
27 port( --clock
28 clk_250MHz : in std_logic;
29 --config inputs
30 start_run : in std_logic;
31 stop_run : in std_logic;
32 general_settings : in std_logic_vector(7 downto 0);
33 maj_coinc_n_phys : in std_logic_vector(5 downto 0);
34 maj_coinc_n_calib : in std_logic_vector(5 downto 0);
35 trigger_delay : in std_logic_vector(9 downto 0);
36 TIM_delay : in std_logic_vector(9 downto 0);
37 dead_time : in std_logic_vector(15 downto 0);
38 --trigger inputs
39 ext_trig_1 : in std_logic;
40 ext_trig_2 : in std_logic;
41 ext_veto : in std_logic;
42 FAD_busy_0 : in std_logic;
43 FAD_busy_1 : in std_logic;
44 FAD_busy_2 : in std_logic;
45 FAD_busy_3 : in std_logic;
46 phys_events : in std_logic_vector(5 downto 0);
47 calib_events : in std_logic_vector(5 downto 0);
48 LP1_pulse : in std_logic;
49 LP2_pulse : in std_logic;
50 PED_pulse : in std_logic;
51 --outputs
52 trigger_ID_done : out std_logic;
53 trigger_ID : out std_logic_vector(55 downto 0);
54 trigger_active : out std_logic;
55 trigger_signal : out std_logic;
56 TIM_signal : out std_logic);
57end trigger_generator;
58
59-- Architecture Definition
60architecture RTL of trigger_generator is
61
62 component deadtime_generator is
63 port( clk_250MHz : in std_logic;
64 deadtime : in std_logic_vector(15 downto 0);
65 start : in std_logic;
66 waiting : out std_logic);
67 end component;
68
69 signal i_deadtime : std_logic;
70
71 component delayed_pulse is
72 generic( pulse_width : integer range 0 to 15);
73 port( clk_250MHz : in std_logic;
74 delay : in std_logic_vector(9 downto 0);
75 input : in std_logic;
76 output : out std_logic);
77 end component;
78
79 signal i_trigger_signal : std_logic;
80 signal i_TIM_signal : std_logic;
81
82 component trigger_ID_count is
83 port( clk_250MHz : in std_logic;
84 start_run : in std_logic;
85 stop_run : in std_logic;
86 maj_coinc_n_phys : in std_logic_vector(5 downto 0);
87 maj_coinc_n_calib : in std_logic_vector(5 downto 0);
88 trigger : in std_logic_vector(8 downto 0);
89 phys_trigger : in std_logic;
90 calib_trigger : in std_logic;
91 internal_trigger : in std_logic_vector(1 downto 0);
92 external_trigger : in std_logic_vector(1 downto 0);
93 trigger_ID_done : out std_logic;
94 trigger_ID : out std_logic_vector(55 downto 0));
95 end component;
96
97 type t_reg is record
98 -- Internal register declaration
99 start_run : std_logic;
100 LP1_delay : std_logic_vector(2 downto 0);
101 LP2_delay : std_logic_vector(2 downto 0);
102 PED_delay : std_logic_vector(2 downto 0);
103 ext_trig_1 : std_logic_vector(2 downto 0);
104 ext_trig_2 : std_logic_vector(2 downto 0);
105 ext_veto : std_logic_vector(1 downto 0);
106 FAD_busy_0 : std_logic_vector(1 downto 0);
107 FAD_busy_1 : std_logic_vector(1 downto 0);
108 FAD_busy_2 : std_logic_vector(1 downto 0);
109 FAD_busy_3 : std_logic_vector(1 downto 0);
110 general_settings : std_logic_vector(7 downto 0);
111 maj_coinc_n_phys : std_logic_vector(5 downto 0);
112 maj_coinc_n_calib : std_logic_vector(5 downto 0);
113 enable_trigger : std_logic;
114 phys_compare : std_logic_vector(1 downto 0);
115 phys_trigger : std_logic;
116 ext_trigger : std_logic_vector(1 downto 0);
117 calib_compare : std_logic_vector(1 downto 0);
118 calib_trigger : std_logic;
119 wait_for_calib : std_logic;
120 internal_trigger : std_logic_vector(1 downto 0);
121 trigger : std_logic_vector(12 downto 0);
122 trigger_active : std_logic;
123 -- Ouput register declaration
124 end record;
125
126 signal i_next_reg : t_reg := (start_run => '0',
127 LP1_delay => (others => '0'),
128 LP2_delay => (others => '0'),
129 PED_delay => (others => '0'),
130 ext_trig_1 => (others => '0'),
131 ext_trig_2 => (others => '0'),
132 ext_veto => (others => '0'),
133 FAD_busy_0 => (others => '0'),
134 FAD_busy_1 => (others => '0'),
135 FAD_busy_2 => (others => '0'),
136 FAD_busy_3 => (others => '0'),
137 general_settings => (others => '0'),
138 maj_coinc_n_phys => (others => '1'),
139 maj_coinc_n_calib => (others => '1'),
140 enable_trigger => '0',
141 phys_compare => (others => '0'),
142 phys_trigger => '0',
143 ext_trigger => (others => '0'),
144 calib_compare => (others => '0'),
145 calib_trigger => '0',
146 wait_for_calib => '0',
147 internal_trigger => (others => '0'),
148 trigger => (others => '0'),
149 trigger_active => '1');
150 signal i_reg : t_reg := (start_run => '0',
151 LP1_delay => (others => '0'),
152 LP2_delay => (others => '0'),
153 PED_delay => (others => '0'),
154 ext_trig_1 => (others => '0'),
155 ext_trig_2 => (others => '0'),
156 ext_veto => (others => '0'),
157 FAD_busy_0 => (others => '0'),
158 FAD_busy_1 => (others => '0'),
159 FAD_busy_2 => (others => '0'),
160 FAD_busy_3 => (others => '0'),
161 general_settings => (others => '0'),
162 maj_coinc_n_phys => (others => '1'),
163 maj_coinc_n_calib => (others => '1'),
164 enable_trigger => '0',
165 phys_compare => (others => '0'),
166 phys_trigger => '0',
167 ext_trigger => (others => '0'),
168 calib_compare => (others => '0'),
169 calib_trigger => '0',
170 wait_for_calib => '0',
171 internal_trigger => (others => '0'),
172 trigger => (others => '0'),
173 trigger_active => '1');
174
175begin
176
177 -- Component instantiation
178 inst_deadtime: deadtime_generator
179 port map( clk_250MHz => clk_250MHz,
180 deadtime => dead_time,
181 start => i_reg.trigger(0),
182 waiting => i_deadtime);
183
184 inst_phys_trig: delayed_pulse
185 generic map( pulse_width => TRIG_SIGNAL_PULSE_WIDTH)
186 port map( clk_250MHz => clk_250MHz,
187 delay => trigger_delay,
188 input => i_reg.trigger(1),
189 output => i_trigger_signal);
190
191 trigger_signal <= i_trigger_signal and i_reg.start_run;
192
193 inst_phys_TIM: delayed_pulse
194 generic map( pulse_width => TIM_SIGNAL_PULSE_WIDTH)
195 port map( clk_250MHz => clk_250MHz,
196 delay => TIM_delay,
197 input => i_reg.trigger(2),
198 output => i_TIM_signal);
199
200 TIM_signal <= i_TIM_signal and i_reg.start_run;
201
202 inst_trig_ID: trigger_ID_count
203 port map( clk_250MHz => clk_250MHz,
204 start_run => start_run,
205 stop_run => stop_run,
206 maj_coinc_n_phys => maj_coinc_n_phys,
207 maj_coinc_n_calib => maj_coinc_n_calib,
208 trigger => i_reg.trigger(12 downto 4),
209 phys_trigger => i_reg.phys_trigger,
210 calib_trigger => i_reg.calib_trigger,
211 internal_trigger => i_reg.internal_trigger,
212 external_trigger => i_reg.ext_trigger,
213 trigger_ID_done => trigger_ID_done,
214 trigger_ID => trigger_ID);
215
216 -- Combinatorial logic
217 process(start_run, general_settings, maj_coinc_n_phys, maj_coinc_n_calib,
218 ext_trig_1, ext_trig_2, ext_veto, FAD_busy_0, FAD_busy_1, FAD_busy_2,
219 FAD_busy_3, phys_events, calib_events, LP1_pulse, LP2_pulse, PED_pulse,
220 i_deadtime, i_reg)
221 variable v_reg : t_reg := (start_run => '0',
222 LP1_delay => (others => '0'),
223 LP2_delay => (others => '0'),
224 PED_delay => (others => '0'),
225 ext_trig_1 => (others => '0'),
226 ext_trig_2 => (others => '0'),
227 ext_veto => (others => '0'),
228 FAD_busy_0 => (others => '0'),
229 FAD_busy_1 => (others => '0'),
230 FAD_busy_2 => (others => '0'),
231 FAD_busy_3 => (others => '0'),
232 general_settings => (others => '0'),
233 maj_coinc_n_phys => (others => '1'),
234 maj_coinc_n_calib => (others => '1'),
235 enable_trigger => '0',
236 phys_compare => (others => '0'),
237 phys_trigger => '0',
238 ext_trigger => (others => '0'),
239 calib_compare => (others => '0'),
240 calib_trigger => '0',
241 wait_for_calib => '0',
242 internal_trigger => (others => '0'),
243 trigger => (others => '0'),
244 trigger_active => '1');
245 begin
246 v_reg := i_reg;
247 --===================================================================================
248
249 --===================================================================================
250 -- External inputs double-sync
251 --===================================================================================
252 v_reg.ext_trig_1(0) := ext_trig_1;
253 v_reg.ext_trig_1(1) := i_reg.ext_trig_1(0);
254 v_reg.ext_trig_1(2) := i_reg.ext_trig_1(1);
255 v_reg.ext_trig_2(0) := ext_trig_2;
256 v_reg.ext_trig_2(1) := i_reg.ext_trig_2(0);
257 v_reg.ext_trig_2(2) := i_reg.ext_trig_2(1);
258 v_reg.ext_veto(0) := ext_veto;
259 v_reg.ext_veto(1) := i_reg.ext_veto(0);
260 v_reg.FAD_busy_0(0) := FAD_busy_0;
261 v_reg.FAD_busy_0(1) := i_reg.FAD_busy_0(0);
262 v_reg.FAD_busy_1(0) := FAD_busy_1;
263 v_reg.FAD_busy_1(1) := i_reg.FAD_busy_1(0);
264 v_reg.FAD_busy_2(0) := FAD_busy_2;
265 v_reg.FAD_busy_2(1) := i_reg.FAD_busy_2(0);
266 v_reg.FAD_busy_3(0) := FAD_busy_3;
267 v_reg.FAD_busy_3(1) := i_reg.FAD_busy_3(0);
268 --===================================================================================
269
270 --===================================================================================
271 -- Re-sync of calibration and pedestal triggers to the 250MHz clock
272 --===================================================================================
273 v_reg.LP1_delay(0) := LP1_pulse;
274 v_reg.LP1_delay(1) := i_reg.LP1_delay(0);
275 v_reg.LP1_delay(2) := i_reg.LP1_delay(1);
276 v_reg.LP2_delay(0) := LP2_pulse;
277 v_reg.LP2_delay(1) := i_reg.LP2_delay(0);
278 v_reg.LP2_delay(2) := i_reg.LP2_delay(1);
279 v_reg.PED_delay(0) := PED_pulse;
280 v_reg.PED_delay(1) := i_reg.PED_delay(0);
281 v_reg.PED_delay(2) := i_reg.PED_delay(1);
282 --===================================================================================
283
284 --===================================================================================
285 -- Settings registration
286 --===================================================================================
287 v_reg.general_settings := general_settings;
288 v_reg.maj_coinc_n_phys := maj_coinc_n_phys;
289 v_reg.maj_coinc_n_calib := maj_coinc_n_calib;
290 --===================================================================================
291
292 --===================================================================================
293 -- Master enable management
294 --===================================================================================
295 v_reg.start_run := start_run;
296 --===================================================================================
297
298 --===================================================================================
299 -- Trigger generation
300 --===================================================================================
301 -- Enable trigger generation only if veto is not active, FAD are not busy and
302 -- deadtime is not enabled
303 if i_reg.trigger(3) = '1' or i_deadtime = '1' or
304 (i_reg.ext_veto(1) = '1' and i_reg.general_settings(1) = '1') or
305 i_reg.FAD_busy_0(1) = '1' or i_reg.FAD_busy_1(1) = '1' or
306 i_reg.FAD_busy_2(1) = '1' or i_reg.FAD_busy_3(1) = '1' then
307 v_reg.enable_trigger := '0';
308 else
309 v_reg.enable_trigger := '1';
310 end if;
311
312 -- Compare number of detected physics event to the physics threshold
313 if phys_events >= i_reg.maj_coinc_n_phys then
314 v_reg.phys_compare(0) := '1';
315 else
316 v_reg.phys_compare(0) := '0';
317 end if;
318 v_reg.phys_compare(1) := i_reg.phys_compare(0);
319
320 -- Activate physics trigger when enabled by settings and physics threhsold is reached
321 if i_reg.general_settings(7) = '1' and i_reg.wait_for_calib = '0' and
322 i_reg.phys_compare(0) = '1' and i_reg.phys_compare(1) = '0' and
323 i_reg.enable_trigger = '1' then
324 v_reg.phys_trigger := '1';
325 else
326 v_reg.phys_trigger := '0';
327 end if;
328
329 -- Lock trigger generator when a pulse on LP1 is detected and wait for FTU events
330 -- counter reach the calibration threshold
331 if i_reg.LP1_delay(1) = '1' and i_reg.LP1_delay(2) = '0' and
332 general_settings(4) = '1' then
333 v_reg.wait_for_calib := '1';
334 elsif i_reg.enable_trigger = '0' then
335 v_reg.wait_for_calib := '0';
336 end if;
337
338 -- Compare number of detected physics event to the calibration threshold
339 if calib_events >= i_reg.maj_coinc_n_calib then
340 v_reg.calib_compare(0) := '1';
341 else
342 v_reg.calib_compare(0) := '0';
343 end if;
344 v_reg.calib_compare(1) := i_reg.calib_compare(0);
345
346 -- Activate calibration trigger when enabled by settings and
347 -- calibration threhsold is reached
348 if i_reg.general_settings(4) = '1' and i_reg.wait_for_calib = '1' and
349 i_reg.calib_compare(0) = '1' and i_reg.calib_compare(1) = '0' and
350 i_reg.enable_trigger = '1' then
351 v_reg.calib_trigger := '1';
352 else
353 v_reg.calib_trigger := '0';
354 end if;
355
356 -- Activate trigger number 1 from external NIM inputs
357 if i_reg.ext_trig_1(1) = '1' and i_reg.ext_trig_1(2) = '0' and
358 i_reg.general_settings(2) = '1' and i_reg.wait_for_calib = '0' and
359 i_reg.enable_trigger = '1' then
360 v_reg.ext_trigger(0) := '1';
361 else
362 v_reg.ext_trigger(0) := '0';
363 end if;
364
365 -- Activate trigger number 2 from external NIM inputs
366 if i_reg.ext_trig_2(1) = '1' and i_reg.ext_trig_2(2) = '0' and
367 i_reg.general_settings(3) = '1' and i_reg.wait_for_calib = '0' and
368 i_reg.enable_trigger = '1' then
369 v_reg.ext_trigger(1) := '1';
370 else
371 v_reg.ext_trigger(1) := '0';
372 end if;
373
374 -- Activate calibration trigger from LP2 pulse
375 if i_reg.LP2_delay(1) = '1' and i_reg.LP2_delay(2) = '0' and
376 i_reg.general_settings(5) = '1' and i_reg.wait_for_calib = '0' and
377 i_reg.enable_trigger = '1' then
378 v_reg.internal_trigger(0) := '1';
379 else
380 v_reg.internal_trigger(0) := '0';
381 end if;
382
383 -- Activate calibration trigger from Pedestal signal
384 if i_reg.PED_delay(1) = '1' and i_reg.PED_delay(2) = '0' and
385 i_reg.general_settings(6) = '1' and i_reg.wait_for_calib = '0' and
386 i_reg.enable_trigger = '1' then
387 v_reg.internal_trigger(1) := '1';
388 else
389 v_reg.internal_trigger(1) := '0';
390 end if;
391
392 -- Generate master trigger for deadtime, trigger and TIM signals,
393 -- triggers counting and ID generation
394 -- It is replicated to limit fanout and improve speed
395 v_reg.trigger(0) := i_reg.phys_trigger or i_reg.calib_trigger or
396 i_reg.ext_trigger(0) or i_reg.ext_trigger(1) or
397 i_reg.internal_trigger(0) or i_reg.internal_trigger(1);
398 v_reg.trigger(1) := v_reg.trigger(0);
399 v_reg.trigger(2) := v_reg.trigger(0);
400 v_reg.trigger(3) := v_reg.trigger(0);
401 v_reg.trigger(4) := v_reg.trigger(0);
402 v_reg.trigger(5) := v_reg.trigger(0);
403 v_reg.trigger(6) := v_reg.trigger(0);
404 v_reg.trigger(7) := v_reg.trigger(0);
405 v_reg.trigger(8) := v_reg.trigger(0);
406 v_reg.trigger(9) := v_reg.trigger(0);
407 v_reg.trigger(10) := v_reg.trigger(0);
408 v_reg.trigger(11) := v_reg.trigger(0);
409 v_reg.trigger(12) := v_reg.trigger(0);
410
411 -- Manage trigger active signal
412 -- Set low when a trigger is processed or FAD are busy or veto is active
413 v_reg.trigger_active := i_reg.enable_trigger and not(i_reg.wait_for_calib);
414 --===================================================================================
415
416 --===================================================================================
417 -- Drive register input
418 i_next_reg <= v_reg;
419
420 --===================================================================================
421 -- Output assignation
422 trigger_active <= i_reg.trigger_active;
423 --===================================================================================
424 end process;
425
426 -- Sequential logic
427 process(clk_250MHz)
428 begin
429 if rising_edge(clk_250MHz) then
430 i_reg <= i_next_reg;
431 end if;
432 end process;
433
434end RTL;
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