| 1 | --=======================================================================================
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| 2 | -- TITLE : Trigger generator
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| 3 | -- DESCRIPTION : Generates triggers from events, calibration pulses or external inputs
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| 4 | -- FILE : trigger_generator.vhd
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| 5 | -- COMPANY : Micro-Cameras & Space Exploration SA
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| 6 | --=======================================================================================
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| 7 | -- CREATION
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| 8 | -- DATE AUTHOR PROJECT REVISION
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| 9 | -- 14/03/2011 JGi 110314a
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| 10 | --=======================================================================================
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| 11 | -- MODIFICATION HISTORY
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| 12 | -- DATE AUTHOR PROJECT REVISION COMMENTS
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| 13 | -- 14/03/2011 JGi 110314a Description
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| 14 | -- 13/04/2011 JGi 110413a Update trigger enable management
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| 15 | --=======================================================================================
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| 16 | -- Library Definition
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| 17 | library ieee;
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| 18 | use ieee.std_logic_1164.all;
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| 19 | use ieee.numeric_std.all;
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| 20 |
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| 21 | library ftm_definitions;
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| 22 | use ftm_definitions.ftm_array_types.all;
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| 23 | use ftm_definitions.ftm_constants.all;
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| 24 |
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| 25 | -- Entity Definition
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| 26 | entity trigger_generator is
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| 27 | port( --clock
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| 28 | clk_250MHz : in std_logic;
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| 29 | --config inputs
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| 30 | start_run : in std_logic;
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| 31 | stop_run : in std_logic;
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| 32 | general_settings : in std_logic_vector(7 downto 0);
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| 33 | maj_coinc_n_phys : in std_logic_vector(5 downto 0);
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| 34 | maj_coinc_n_calib : in std_logic_vector(5 downto 0);
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| 35 | trigger_delay : in std_logic_vector(9 downto 0);
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| 36 | TIM_delay : in std_logic_vector(9 downto 0);
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| 37 | dead_time : in std_logic_vector(15 downto 0);
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| 38 | --trigger inputs
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| 39 | ext_trig_1 : in std_logic;
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| 40 | ext_trig_2 : in std_logic;
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| 41 | ext_veto : in std_logic;
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| 42 | FAD_busy_0 : in std_logic;
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| 43 | FAD_busy_1 : in std_logic;
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| 44 | FAD_busy_2 : in std_logic;
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| 45 | FAD_busy_3 : in std_logic;
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| 46 | phys_events : in std_logic_vector(5 downto 0);
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| 47 | calib_events : in std_logic_vector(5 downto 0);
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| 48 | LP1_pulse : in std_logic;
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| 49 | LP2_pulse : in std_logic;
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| 50 | PED_pulse : in std_logic;
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| 51 | --outputs
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| 52 | trigger_ID_done : out std_logic;
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| 53 | trigger_ID : out std_logic_vector(55 downto 0);
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| 54 | trigger_active : out std_logic;
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| 55 | trigger_signal : out std_logic;
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| 56 | TIM_signal : out std_logic);
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| 57 | end trigger_generator;
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| 58 |
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| 59 | -- Architecture Definition
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| 60 | architecture RTL of trigger_generator is
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| 61 |
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| 62 | component deadtime_generator is
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| 63 | port( clk_250MHz : in std_logic;
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| 64 | deadtime : in std_logic_vector(15 downto 0);
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| 65 | start : in std_logic;
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| 66 | waiting : out std_logic);
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| 67 | end component;
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| 68 |
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| 69 | signal i_deadtime : std_logic;
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| 70 |
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| 71 | component delayed_pulse is
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| 72 | generic( pulse_width : integer range 0 to 15);
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| 73 | port( clk_250MHz : in std_logic;
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| 74 | delay : in std_logic_vector(9 downto 0);
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| 75 | input : in std_logic;
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| 76 | output : out std_logic);
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| 77 | end component;
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| 78 |
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| 79 | signal i_trigger_signal : std_logic;
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| 80 | signal i_TIM_signal : std_logic;
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| 81 |
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| 82 | component trigger_ID_count is
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| 83 | port( clk_250MHz : in std_logic;
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| 84 | start_run : in std_logic;
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| 85 | stop_run : in std_logic;
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| 86 | maj_coinc_n_phys : in std_logic_vector(5 downto 0);
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| 87 | maj_coinc_n_calib : in std_logic_vector(5 downto 0);
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| 88 | trigger : in std_logic_vector(8 downto 0);
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| 89 | phys_trigger : in std_logic;
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| 90 | calib_trigger : in std_logic;
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| 91 | internal_trigger : in std_logic_vector(1 downto 0);
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| 92 | external_trigger : in std_logic_vector(1 downto 0);
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| 93 | trigger_ID_done : out std_logic;
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| 94 | trigger_ID : out std_logic_vector(55 downto 0));
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| 95 | end component;
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| 96 |
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| 97 | type t_reg is record
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| 98 | -- Internal register declaration
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| 99 | start_run : std_logic;
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| 100 | LP1_delay : std_logic_vector(2 downto 0);
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| 101 | LP2_delay : std_logic_vector(2 downto 0);
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| 102 | PED_delay : std_logic_vector(2 downto 0);
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| 103 | ext_trig_1 : std_logic_vector(2 downto 0);
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| 104 | ext_trig_2 : std_logic_vector(2 downto 0);
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| 105 | ext_veto : std_logic_vector(1 downto 0);
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| 106 | FAD_busy_0 : std_logic_vector(1 downto 0);
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| 107 | FAD_busy_1 : std_logic_vector(1 downto 0);
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| 108 | FAD_busy_2 : std_logic_vector(1 downto 0);
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| 109 | FAD_busy_3 : std_logic_vector(1 downto 0);
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| 110 | general_settings : std_logic_vector(7 downto 0);
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| 111 | maj_coinc_n_phys : std_logic_vector(5 downto 0);
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| 112 | maj_coinc_n_calib : std_logic_vector(5 downto 0);
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| 113 | enable_trigger : std_logic;
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| 114 | phys_compare : std_logic_vector(1 downto 0);
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| 115 | phys_trigger : std_logic;
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| 116 | ext_trigger : std_logic_vector(1 downto 0);
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| 117 | calib_compare : std_logic_vector(1 downto 0);
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| 118 | calib_trigger : std_logic;
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| 119 | wait_for_calib : std_logic;
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| 120 | internal_trigger : std_logic_vector(1 downto 0);
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| 121 | trigger : std_logic_vector(12 downto 0);
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| 122 | trigger_active : std_logic;
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| 123 | -- Ouput register declaration
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| 124 | end record;
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| 125 |
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| 126 | signal i_next_reg : t_reg := (start_run => '0',
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| 127 | LP1_delay => (others => '0'),
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| 128 | LP2_delay => (others => '0'),
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| 129 | PED_delay => (others => '0'),
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| 130 | ext_trig_1 => (others => '0'),
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| 131 | ext_trig_2 => (others => '0'),
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| 132 | ext_veto => (others => '0'),
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| 133 | FAD_busy_0 => (others => '0'),
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| 134 | FAD_busy_1 => (others => '0'),
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| 135 | FAD_busy_2 => (others => '0'),
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| 136 | FAD_busy_3 => (others => '0'),
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| 137 | general_settings => (others => '0'),
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| 138 | maj_coinc_n_phys => (others => '1'),
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| 139 | maj_coinc_n_calib => (others => '1'),
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| 140 | enable_trigger => '0',
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| 141 | phys_compare => (others => '0'),
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| 142 | phys_trigger => '0',
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| 143 | ext_trigger => (others => '0'),
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| 144 | calib_compare => (others => '0'),
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| 145 | calib_trigger => '0',
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| 146 | wait_for_calib => '0',
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| 147 | internal_trigger => (others => '0'),
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| 148 | trigger => (others => '0'),
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| 149 | trigger_active => '1');
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| 150 | signal i_reg : t_reg := (start_run => '0',
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| 151 | LP1_delay => (others => '0'),
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| 152 | LP2_delay => (others => '0'),
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| 153 | PED_delay => (others => '0'),
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| 154 | ext_trig_1 => (others => '0'),
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| 155 | ext_trig_2 => (others => '0'),
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| 156 | ext_veto => (others => '0'),
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| 157 | FAD_busy_0 => (others => '0'),
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| 158 | FAD_busy_1 => (others => '0'),
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| 159 | FAD_busy_2 => (others => '0'),
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| 160 | FAD_busy_3 => (others => '0'),
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| 161 | general_settings => (others => '0'),
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| 162 | maj_coinc_n_phys => (others => '1'),
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| 163 | maj_coinc_n_calib => (others => '1'),
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| 164 | enable_trigger => '0',
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| 165 | phys_compare => (others => '0'),
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| 166 | phys_trigger => '0',
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| 167 | ext_trigger => (others => '0'),
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| 168 | calib_compare => (others => '0'),
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| 169 | calib_trigger => '0',
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| 170 | wait_for_calib => '0',
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| 171 | internal_trigger => (others => '0'),
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| 172 | trigger => (others => '0'),
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| 173 | trigger_active => '1');
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| 174 |
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| 175 | begin
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| 176 |
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| 177 | -- Component instantiation
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| 178 | inst_deadtime: deadtime_generator
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| 179 | port map( clk_250MHz => clk_250MHz,
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| 180 | deadtime => dead_time,
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| 181 | start => i_reg.trigger(0),
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| 182 | waiting => i_deadtime);
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| 183 |
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| 184 | inst_phys_trig: delayed_pulse
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| 185 | generic map( pulse_width => TRIG_SIGNAL_PULSE_WIDTH)
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| 186 | port map( clk_250MHz => clk_250MHz,
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| 187 | delay => trigger_delay,
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| 188 | input => i_reg.trigger(1),
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| 189 | output => i_trigger_signal);
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| 190 |
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| 191 | trigger_signal <= i_trigger_signal and i_reg.start_run;
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| 192 |
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| 193 | inst_phys_TIM: delayed_pulse
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| 194 | generic map( pulse_width => TIM_SIGNAL_PULSE_WIDTH)
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| 195 | port map( clk_250MHz => clk_250MHz,
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| 196 | delay => TIM_delay,
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| 197 | input => i_reg.trigger(2),
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| 198 | output => i_TIM_signal);
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| 199 |
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| 200 | TIM_signal <= i_TIM_signal and i_reg.start_run;
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| 201 |
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| 202 | inst_trig_ID: trigger_ID_count
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| 203 | port map( clk_250MHz => clk_250MHz,
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| 204 | start_run => start_run,
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| 205 | stop_run => stop_run,
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| 206 | maj_coinc_n_phys => maj_coinc_n_phys,
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| 207 | maj_coinc_n_calib => maj_coinc_n_calib,
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| 208 | trigger => i_reg.trigger(12 downto 4),
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| 209 | phys_trigger => i_reg.phys_trigger,
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| 210 | calib_trigger => i_reg.calib_trigger,
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| 211 | internal_trigger => i_reg.internal_trigger,
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| 212 | external_trigger => i_reg.ext_trigger,
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| 213 | trigger_ID_done => trigger_ID_done,
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| 214 | trigger_ID => trigger_ID);
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| 215 |
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| 216 | -- Combinatorial logic
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| 217 | process(start_run, general_settings, maj_coinc_n_phys, maj_coinc_n_calib,
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| 218 | ext_trig_1, ext_trig_2, ext_veto, FAD_busy_0, FAD_busy_1, FAD_busy_2,
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| 219 | FAD_busy_3, phys_events, calib_events, LP1_pulse, LP2_pulse, PED_pulse,
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| 220 | i_deadtime, i_reg)
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| 221 | variable v_reg : t_reg := (start_run => '0',
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| 222 | LP1_delay => (others => '0'),
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| 223 | LP2_delay => (others => '0'),
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| 224 | PED_delay => (others => '0'),
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| 225 | ext_trig_1 => (others => '0'),
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| 226 | ext_trig_2 => (others => '0'),
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| 227 | ext_veto => (others => '0'),
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| 228 | FAD_busy_0 => (others => '0'),
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| 229 | FAD_busy_1 => (others => '0'),
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| 230 | FAD_busy_2 => (others => '0'),
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| 231 | FAD_busy_3 => (others => '0'),
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| 232 | general_settings => (others => '0'),
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| 233 | maj_coinc_n_phys => (others => '1'),
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| 234 | maj_coinc_n_calib => (others => '1'),
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| 235 | enable_trigger => '0',
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| 236 | phys_compare => (others => '0'),
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| 237 | phys_trigger => '0',
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| 238 | ext_trigger => (others => '0'),
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| 239 | calib_compare => (others => '0'),
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| 240 | calib_trigger => '0',
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| 241 | wait_for_calib => '0',
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| 242 | internal_trigger => (others => '0'),
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| 243 | trigger => (others => '0'),
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| 244 | trigger_active => '1');
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| 245 | begin
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| 246 | v_reg := i_reg;
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| 247 | --===================================================================================
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| 248 |
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| 249 | --===================================================================================
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| 250 | -- External inputs double-sync
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| 251 | --===================================================================================
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| 252 | v_reg.ext_trig_1(0) := ext_trig_1;
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| 253 | v_reg.ext_trig_1(1) := i_reg.ext_trig_1(0);
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| 254 | v_reg.ext_trig_1(2) := i_reg.ext_trig_1(1);
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| 255 | v_reg.ext_trig_2(0) := ext_trig_2;
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| 256 | v_reg.ext_trig_2(1) := i_reg.ext_trig_2(0);
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| 257 | v_reg.ext_trig_2(2) := i_reg.ext_trig_2(1);
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| 258 | v_reg.ext_veto(0) := ext_veto;
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| 259 | v_reg.ext_veto(1) := i_reg.ext_veto(0);
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| 260 | v_reg.FAD_busy_0(0) := FAD_busy_0;
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| 261 | v_reg.FAD_busy_0(1) := i_reg.FAD_busy_0(0);
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| 262 | v_reg.FAD_busy_1(0) := FAD_busy_1;
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| 263 | v_reg.FAD_busy_1(1) := i_reg.FAD_busy_1(0);
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| 264 | v_reg.FAD_busy_2(0) := FAD_busy_2;
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| 265 | v_reg.FAD_busy_2(1) := i_reg.FAD_busy_2(0);
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| 266 | v_reg.FAD_busy_3(0) := FAD_busy_3;
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| 267 | v_reg.FAD_busy_3(1) := i_reg.FAD_busy_3(0);
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| 268 | --===================================================================================
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| 269 |
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| 270 | --===================================================================================
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| 271 | -- Re-sync of calibration and pedestal triggers to the 250MHz clock
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| 272 | --===================================================================================
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| 273 | v_reg.LP1_delay(0) := LP1_pulse;
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| 274 | v_reg.LP1_delay(1) := i_reg.LP1_delay(0);
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| 275 | v_reg.LP1_delay(2) := i_reg.LP1_delay(1);
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| 276 | v_reg.LP2_delay(0) := LP2_pulse;
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| 277 | v_reg.LP2_delay(1) := i_reg.LP2_delay(0);
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| 278 | v_reg.LP2_delay(2) := i_reg.LP2_delay(1);
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| 279 | v_reg.PED_delay(0) := PED_pulse;
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| 280 | v_reg.PED_delay(1) := i_reg.PED_delay(0);
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| 281 | v_reg.PED_delay(2) := i_reg.PED_delay(1);
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| 282 | --===================================================================================
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| 283 |
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| 284 | --===================================================================================
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| 285 | -- Settings registration
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| 286 | --===================================================================================
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| 287 | v_reg.general_settings := general_settings;
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| 288 | v_reg.maj_coinc_n_phys := maj_coinc_n_phys;
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| 289 | v_reg.maj_coinc_n_calib := maj_coinc_n_calib;
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| 290 | --===================================================================================
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| 291 |
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| 292 | --===================================================================================
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| 293 | -- Master enable management
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| 294 | --===================================================================================
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| 295 | v_reg.start_run := start_run;
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| 296 | --===================================================================================
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| 297 |
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| 298 | --===================================================================================
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| 299 | -- Trigger generation
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| 300 | --===================================================================================
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| 301 | -- Enable trigger generation only if veto is not active, FAD are not busy and
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| 302 | -- deadtime is not enabled
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| 303 | if i_reg.trigger(3) = '1' or i_deadtime = '1' or
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| 304 | (i_reg.ext_veto(1) = '1' and i_reg.general_settings(1) = '1') or
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| 305 | i_reg.FAD_busy_0(1) = '1' or i_reg.FAD_busy_1(1) = '1' or
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| 306 | i_reg.FAD_busy_2(1) = '1' or i_reg.FAD_busy_3(1) = '1' then
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| 307 | v_reg.enable_trigger := '0';
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| 308 | else
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| 309 | v_reg.enable_trigger := '1';
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| 310 | end if;
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| 311 |
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| 312 | -- Compare number of detected physics event to the physics threshold
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| 313 | if phys_events >= i_reg.maj_coinc_n_phys then
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| 314 | v_reg.phys_compare(0) := '1';
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| 315 | else
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| 316 | v_reg.phys_compare(0) := '0';
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| 317 | end if;
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| 318 | v_reg.phys_compare(1) := i_reg.phys_compare(0);
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| 319 |
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| 320 | -- Activate physics trigger when enabled by settings and physics threhsold is reached
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| 321 | if i_reg.general_settings(7) = '1' and i_reg.wait_for_calib = '0' and
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| 322 | i_reg.phys_compare(0) = '1' and i_reg.phys_compare(1) = '0' and
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| 323 | i_reg.enable_trigger = '1' then
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| 324 | v_reg.phys_trigger := '1';
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| 325 | else
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| 326 | v_reg.phys_trigger := '0';
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| 327 | end if;
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| 328 |
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| 329 | -- Lock trigger generator when a pulse on LP1 is detected and wait for FTU events
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| 330 | -- counter reach the calibration threshold
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| 331 | if i_reg.LP1_delay(1) = '1' and i_reg.LP1_delay(2) = '0' and
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| 332 | general_settings(4) = '1' then
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| 333 | v_reg.wait_for_calib := '1';
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| 334 | elsif i_reg.enable_trigger = '0' then
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| 335 | v_reg.wait_for_calib := '0';
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| 336 | end if;
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| 337 |
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| 338 | -- Compare number of detected physics event to the calibration threshold
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| 339 | if calib_events >= i_reg.maj_coinc_n_calib then
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| 340 | v_reg.calib_compare(0) := '1';
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| 341 | else
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| 342 | v_reg.calib_compare(0) := '0';
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| 343 | end if;
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| 344 | v_reg.calib_compare(1) := i_reg.calib_compare(0);
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| 345 |
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| 346 | -- Activate calibration trigger when enabled by settings and
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| 347 | -- calibration threhsold is reached
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| 348 | if i_reg.general_settings(4) = '1' and i_reg.wait_for_calib = '1' and
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| 349 | i_reg.calib_compare(0) = '1' and i_reg.calib_compare(1) = '0' and
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| 350 | i_reg.enable_trigger = '1' then
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| 351 | v_reg.calib_trigger := '1';
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| 352 | else
|
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| 353 | v_reg.calib_trigger := '0';
|
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| 354 | end if;
|
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| 355 |
|
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| 356 | -- Activate trigger number 1 from external NIM inputs
|
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| 357 | if i_reg.ext_trig_1(1) = '1' and i_reg.ext_trig_1(2) = '0' and
|
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| 358 | i_reg.general_settings(2) = '1' and i_reg.wait_for_calib = '0' and
|
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| 359 | i_reg.enable_trigger = '1' then
|
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| 360 | v_reg.ext_trigger(0) := '1';
|
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| 361 | else
|
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| 362 | v_reg.ext_trigger(0) := '0';
|
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| 363 | end if;
|
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| 364 |
|
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| 365 | -- Activate trigger number 2 from external NIM inputs
|
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| 366 | if i_reg.ext_trig_2(1) = '1' and i_reg.ext_trig_2(2) = '0' and
|
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| 367 | i_reg.general_settings(3) = '1' and i_reg.wait_for_calib = '0' and
|
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| 368 | i_reg.enable_trigger = '1' then
|
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| 369 | v_reg.ext_trigger(1) := '1';
|
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| 370 | else
|
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| 371 | v_reg.ext_trigger(1) := '0';
|
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| 372 | end if;
|
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| 373 |
|
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| 374 | -- Activate calibration trigger from LP2 pulse
|
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| 375 | if i_reg.LP2_delay(1) = '1' and i_reg.LP2_delay(2) = '0' and
|
|---|
| 376 | i_reg.general_settings(5) = '1' and i_reg.wait_for_calib = '0' and
|
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| 377 | i_reg.enable_trigger = '1' then
|
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| 378 | v_reg.internal_trigger(0) := '1';
|
|---|
| 379 | else
|
|---|
| 380 | v_reg.internal_trigger(0) := '0';
|
|---|
| 381 | end if;
|
|---|
| 382 |
|
|---|
| 383 | -- Activate calibration trigger from Pedestal signal
|
|---|
| 384 | if i_reg.PED_delay(1) = '1' and i_reg.PED_delay(2) = '0' and
|
|---|
| 385 | i_reg.general_settings(6) = '1' and i_reg.wait_for_calib = '0' and
|
|---|
| 386 | i_reg.enable_trigger = '1' then
|
|---|
| 387 | v_reg.internal_trigger(1) := '1';
|
|---|
| 388 | else
|
|---|
| 389 | v_reg.internal_trigger(1) := '0';
|
|---|
| 390 | end if;
|
|---|
| 391 |
|
|---|
| 392 | -- Generate master trigger for deadtime, trigger and TIM signals,
|
|---|
| 393 | -- triggers counting and ID generation
|
|---|
| 394 | -- It is replicated to limit fanout and improve speed
|
|---|
| 395 | v_reg.trigger(0) := i_reg.phys_trigger or i_reg.calib_trigger or
|
|---|
| 396 | i_reg.ext_trigger(0) or i_reg.ext_trigger(1) or
|
|---|
| 397 | i_reg.internal_trigger(0) or i_reg.internal_trigger(1);
|
|---|
| 398 | v_reg.trigger(1) := v_reg.trigger(0);
|
|---|
| 399 | v_reg.trigger(2) := v_reg.trigger(0);
|
|---|
| 400 | v_reg.trigger(3) := v_reg.trigger(0);
|
|---|
| 401 | v_reg.trigger(4) := v_reg.trigger(0);
|
|---|
| 402 | v_reg.trigger(5) := v_reg.trigger(0);
|
|---|
| 403 | v_reg.trigger(6) := v_reg.trigger(0);
|
|---|
| 404 | v_reg.trigger(7) := v_reg.trigger(0);
|
|---|
| 405 | v_reg.trigger(8) := v_reg.trigger(0);
|
|---|
| 406 | v_reg.trigger(9) := v_reg.trigger(0);
|
|---|
| 407 | v_reg.trigger(10) := v_reg.trigger(0);
|
|---|
| 408 | v_reg.trigger(11) := v_reg.trigger(0);
|
|---|
| 409 | v_reg.trigger(12) := v_reg.trigger(0);
|
|---|
| 410 |
|
|---|
| 411 | -- Manage trigger active signal
|
|---|
| 412 | -- Set low when a trigger is processed or FAD are busy or veto is active
|
|---|
| 413 | v_reg.trigger_active := i_reg.enable_trigger and not(i_reg.wait_for_calib);
|
|---|
| 414 | --===================================================================================
|
|---|
| 415 |
|
|---|
| 416 | --===================================================================================
|
|---|
| 417 | -- Drive register input
|
|---|
| 418 | i_next_reg <= v_reg;
|
|---|
| 419 |
|
|---|
| 420 | --===================================================================================
|
|---|
| 421 | -- Output assignation
|
|---|
| 422 | trigger_active <= i_reg.trigger_active;
|
|---|
| 423 | --===================================================================================
|
|---|
| 424 | end process;
|
|---|
| 425 |
|
|---|
| 426 | -- Sequential logic
|
|---|
| 427 | process(clk_250MHz)
|
|---|
| 428 | begin
|
|---|
| 429 | if rising_edge(clk_250MHz) then
|
|---|
| 430 | i_reg <= i_next_reg;
|
|---|
| 431 | end if;
|
|---|
| 432 | end process;
|
|---|
| 433 |
|
|---|
| 434 | end RTL; |
|---|
