source: firmware/FTU/FTU_control.vhd@ 10009

Last change on this file since 10009 was 10009, checked in by weitzel, 14 years ago
DNA identifier added and RS485 debugged
File size: 28.0 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 08/06/2010
6-- Design Name:
7-- Module Name: FTU_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Control FSM of FACT FTU board
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20
21library IEEE;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.STD_LOGIC_ARITH.ALL;
24use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
26library ftu_definitions;
27USE ftu_definitions.ftu_array_types.all;
28USE ftu_definitions.ftu_constants.all;
29
30---- Uncomment the following library declaration if instantiating
31---- any Xilinx primitives in this code.
32--library UNISIM;
33--use UNISIM.VComponents.all;
34
35entity FTU_control is
36 port(
37 clk_50MHz : IN std_logic;
38 clk_ready : IN std_logic; -- from DCM
39 config_started : IN std_logic; -- from DAC/SPI
40 config_ready : IN std_logic; -- from DAC/SPI
41 ram_doa : IN STD_LOGIC_VECTOR(7 downto 0);
42 ram_dob : IN STD_LOGIC_VECTOR(15 downto 0);
43 rate_array : IN rate_array_type; -- from counters
44 overflow_array : IN STD_LOGIC_VECTOR(7 downto 0); -- from counters
45 new_rates : IN std_logic; -- from counters
46 new_DACs : IN std_logic; -- from RS485 module
47 new_enables : IN std_logic; -- from RS485 module
48 new_prescaling : IN std_logic; -- from RS485 module
49 read_rates : IN std_logic; -- from RS485 module
50 read_DACs : IN std_logic; -- from RS485 module
51 read_enables : IN std_logic; -- from RS485 module
52 read_prescaling : IN std_logic; -- from RS485 module
53 ping_pong : IN std_logic; -- from RS485 module
54 dac_array_rs485_out : IN dac_array_type; -- from RS485 module
55 enable_array_rs485_out : IN enable_array_type; -- from RS485 module
56 prescaling_rs485_out : IN STD_LOGIC_VECTOR(7 downto 0); -- from RS485 module
57 dna_ready : IN std_logic; -- from FTU_dna_gen
58 reset : OUT std_logic;
59 config_start : OUT std_logic;
60 ram_ena : OUT std_logic;
61 ram_enb : OUT std_logic;
62 ram_wea : OUT STD_LOGIC_VECTOR(0 downto 0);
63 ram_web : OUT STD_LOGIC_VECTOR(0 downto 0);
64 ram_ada : OUT STD_LOGIC_VECTOR(4 downto 0);
65 ram_adb : OUT STD_LOGIC_VECTOR(3 downto 0);
66 ram_dia : OUT STD_LOGIC_VECTOR(7 downto 0);
67 ram_dib : OUT STD_LOGIC_VECTOR(15 downto 0);
68 rate_array_rs485 : OUT rate_array_type := (0,0,0,0,0); -- to RS485 module
69 overflow_array_rs485_in : OUT STD_LOGIC_VECTOR(7 downto 0) := "00000000"; -- to RS485 module
70 rates_ready : OUT std_logic := '0'; -- to RS485 module
71 DACs_ready : OUT std_logic := '0'; -- to RS485 module
72 enables_ready : OUT std_logic := '0'; -- to RS485 module
73 prescaling_ready : OUT std_logic := '0'; -- to RS485 module
74 ping_pong_ready : OUT std_logic := '0'; -- to RS485 module
75 dac_array : OUT dac_array_type;
76 enable_array : OUT enable_array_type;
77 cntr_reset : OUT STD_LOGIC;
78 prescaling : OUT STD_LOGIC_VECTOR(7 downto 0);
79 dna_start : OUT std_logic := '0' -- to FTU_dna_gen
80 );
81end FTU_control;
82
83architecture Behavioral of FTU_control is
84
85 signal reset_sig : STD_LOGIC := '0'; --initialize reset to 0 at power up
86
87 --DAC/SPI interface, default DACs come from RAM during INIT
88 signal config_start_sig : STD_LOGIC := '0';
89 signal dac_array_sig : dac_array_type := (0,0,0,0,0,0,0,0);
90
91 --enable signals for pixels in trigger, default values come from RAM during INIT
92 signal enable_array_sig : enable_array_type := ("0000000000000000", --patch A
93 "0000000000000000", --patch B
94 "0000000000000000", --patch C
95 "0000000000000000");--patch D
96
97 signal rate_array_sig : rate_array_type; -- initialized in FTU_top
98 signal cntr_reset_sig : STD_LOGIC := '0';
99 signal prescaling_sig : STD_LOGIC_VECTOR(7 downto 0) := "00011101"; -- 29
100
101 signal ram_ena_sig : STD_LOGIC := '0'; -- RAM enable for port A
102 signal ram_enb_sig : STD_LOGIC := '0'; -- RAM enable for port B
103 signal ram_wea_sig : STD_LOGIC_VECTOR(0 downto 0) := "0"; -- RAM write enable for port A
104 signal ram_web_sig : STD_LOGIC_VECTOR(0 downto 0) := "0"; -- RAM write enable for port B
105 signal ram_ada_sig : STD_LOGIC_VECTOR(4 downto 0) := (others => '0'); --RAM port A address
106 signal ram_adb_sig : STD_LOGIC_VECTOR(3 downto 0) := (others => '0'); --RAM port B address
107 signal ram_dia_sig : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); --RAM data in A
108 signal ram_dib_sig : STD_LOGIC_VECTOR(15 downto 0) := (others => '0'); --RAM data in B
109
110 --counter to loop through RAM
111 signal ram_ada_cntr : INTEGER range 0 to 2**RAM_ADDR_WIDTH_A := 0;
112 signal ram_dac_cntr : INTEGER range 0 to (NO_OF_DAC - NO_OF_DAC_NOT_USED + 2) := 0;
113 signal ram_enable_cntr : INTEGER range 0 to (NO_OF_ENABLE + 1) := 0;
114 signal ram_counter_cntr : INTEGER range 0 to (NO_OF_COUNTER + 2) := 0; --includes overflow register
115
116 signal wait_cntr : INTEGER range 0 to 2**RAM_ADDR_WIDTH_A := 0;
117
118 signal new_rates_sig : STD_LOGIC := '0';
119 signal new_rates_busy : STD_LOGIC := '1'; -- veto the writing of new rates until in RUNNING
120
121 signal new_DACs_in_RAM : STD_LOGIC := '0';
122 signal new_enables_in_RAM : STD_LOGIC := '0';
123 signal new_prescaling_in_RAM : STD_LOGIC := '0';
124
125 type FTU_control_StateType is (IDLE, INIT_RAM, INIT_DNA, RUNNING,
126 CONFIG_ENABLE, CONFIG_DAC, CONFIG_DAC_WAIT, CONFIG_COUNTER,
127 WRITE_RATES, WRITE_DAC, WRITE_ENABLE, WRITE_PRESCALING,
128 READOUT_RATES, READOUT_DAC, READOUT_ENABLE, READOUT_PRESCALING,
129 DO_PING_PONG);
130 signal FTU_control_State : FTU_control_StateType;
131
132begin
133
134 --FTU control finite state machine
135
136 FTU_control_FSM: process (clk_50MHz)
137
138 begin
139
140 reset_sig <= '0';
141
142 if Rising_edge(clk_50MHz) then
143
144 case FTU_control_State is
145
146 when IDLE => -- wait for DCMs to lock
147 if (clk_ready = '1') then
148 FTU_control_State <= INIT_DNA;
149 else
150 FTU_control_State <= IDLE;
151 end if;
152
153 when INIT_DNA => -- determine FPGA DNA
154 if (dna_ready = '1') then
155 FTU_control_State <= INIT_RAM;
156 dna_start <= '0';
157 else
158 dna_start <= '1';
159 FTU_control_State <= INIT_DNA;
160 end if;
161
162 when INIT_RAM => -- load default config data to RAM, see also ftu_definitions.vhd for more info
163 ram_ena_sig <= '1';
164 ram_wea_sig <= "1";
165 ram_ada_cntr <= ram_ada_cntr + 1;
166 ram_ada_sig <= conv_std_logic_vector(ram_ada_cntr, RAM_ADDR_WIDTH_A);
167 if (ram_ada_cntr < NO_OF_ENABLE*RAM_ADDR_RATIO) then -- default enables
168 if (ram_ada_cntr mod 2 = 0) then
169 ram_dia_sig <= DEFAULT_ENABLE(ram_ada_cntr / 2)(7 downto 0);
170 else
171 ram_dia_sig <= DEFAULT_ENABLE(ram_ada_cntr / 2)(15 downto 8);
172 end if;
173 FTU_control_State <= INIT_RAM;
174 elsif (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) then -- default counter values
175 ram_dia_sig <= (others => '0');
176 FTU_control_State <= INIT_RAM;
177 elsif (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO)) then -- default DACs
178 if (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)*RAM_ADDR_RATIO)) then
179 if (ram_ada_cntr mod 2 = 0) then
180 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) / 2),16)(7 downto 0);
181 else
182 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) / 2),16)(15 downto 8);
183 end if;
184 else
185 if (ram_ada_cntr mod 2 = 0) then
186 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC(((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) / 2) + NO_OF_DAC_NOT_USED),16)(7 downto 0);
187 else
188 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC(((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) / 2) + NO_OF_DAC_NOT_USED),16)(15 downto 8);
189 end if;
190 end if;
191 FTU_control_State <= INIT_RAM;
192 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO)) then -- default prescaling
193 ram_dia_sig <= conv_std_logic_vector(DEFAULT_PRESCALING,8);
194 FTU_control_State <= INIT_RAM;
195 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 1) then -- default overflow register
196 ram_dia_sig <= (others => '0');
197 FTU_control_State <= INIT_RAM;
198 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 2) then -- default checksum
199 ram_dia_sig <= (others => '0');
200 FTU_control_State <= INIT_RAM;
201 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 3) then -- empty RAM cell
202 ram_dia_sig <= (others => '0');
203 FTU_control_State <= INIT_RAM;
204 else
205 ram_dia_sig <= (others => '0');
206 ram_ada_cntr <= 0;
207 ram_ada_sig <= (others => '0');
208 ram_ena_sig <= '0';
209 ram_wea_sig <= "0";
210 new_DACs_in_RAM <= '1';
211 new_enables_in_RAM <= '1';
212 new_prescaling_in_RAM <= '1';
213 cntr_reset_sig <= '1';
214 new_rates_busy <= '0';
215 FTU_control_State <= RUNNING;
216 end if;
217
218 when RUNNING => -- count triggers and react to commands from FTM
219 cntr_reset_sig <= '0';
220 config_start_sig <= '0';
221 if (new_rates_sig = '1') then -- counters have finished a period
222 FTU_control_State <= WRITE_RATES;
223 else -- update FTU settings if necessary
224 if (new_DACs_in_RAM = '1') then
225 ram_enb_sig <= '1';
226 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER), RAM_ADDR_WIDTH_B);
227 FTU_control_State <= CONFIG_DAC;
228 elsif (new_DACs_in_RAM = '0' and new_enables_in_RAM = '1') then
229 ram_enb_sig <= '1';
230 ram_adb_sig <= conv_std_logic_vector(0, RAM_ADDR_WIDTH_B);
231 FTU_control_State <= CONFIG_ENABLE;
232 elsif (new_DACs_in_RAM = '0' and new_enables_in_RAM = '0' and new_prescaling_in_RAM = '1') then
233 ram_ena_sig <= '1';
234 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A);
235 FTU_control_State <= CONFIG_COUNTER;
236 else -- nothing to be updated, check new commands from RS485
237 if (new_DACs = '1') then
238 FTU_control_State <= WRITE_DAC;
239 elsif (new_DACs = '0' and new_enables = '1') then
240 FTU_control_State <= WRITE_ENABLE;
241 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '1') then
242 FTU_control_State <= WRITE_PRESCALING;
243 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and
244 read_rates = '1') then
245 ram_enb_sig <= '1';
246 ram_adb_sig <= conv_std_logic_vector(NO_OF_ENABLE, RAM_ADDR_WIDTH_B);
247 FTU_control_State <= READOUT_RATES;
248 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and
249 read_rates = '0' and read_DACs = '1') then
250 ram_enb_sig <= '1';
251 ram_adb_sig <= conv_std_logic_vector(NO_OF_ENABLE + NO_OF_COUNTER, RAM_ADDR_WIDTH_B);
252 FTU_control_State <= READOUT_DAC;
253 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and
254 read_rates = '0' and read_DACs = '0' and read_enables = '1') then
255 ram_enb_sig <= '1';
256 ram_adb_sig <= conv_std_logic_vector(0, RAM_ADDR_WIDTH_B);
257 FTU_control_State <= READOUT_ENABLE;
258 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and
259 read_rates = '0' and read_DACs = '0' and read_enables = '0' and read_prescaling = '1') then
260 ram_ena_sig <= '1';
261 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A);
262 FTU_control_State <= READOUT_PRESCALING;
263 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and
264 read_rates = '0' and read_DACs = '0' and read_enables = '0' and read_prescaling = '0' and
265 ping_pong = '1') then
266 FTU_control_State <= DO_PING_PONG;
267 else
268 FTU_control_State <= RUNNING; --no commands from RS485 -> stay running
269 end if;
270 end if;
271 end if;
272
273 when CONFIG_COUNTER =>
274 wait_cntr <= wait_cntr + 1;
275 new_rates_busy <= '1';
276 if (wait_cntr = 0) then
277 FTU_control_State <= CONFIG_COUNTER;
278 elsif (wait_cntr = 1) then
279 prescaling_sig <= ram_doa;
280 FTU_control_State <= CONFIG_COUNTER;
281 prescaling_ready <= '1';
282 else
283 cntr_reset_sig <= '1';
284 ram_ada_sig <= (others => '0');
285 wait_cntr <= 0;
286 new_prescaling_in_RAM <= '0';
287 ram_ena_sig <= '0';
288 new_rates_busy <= '0';
289 prescaling_ready <= '0';
290 FTU_control_State <= RUNNING;
291 end if;
292
293 when CONFIG_ENABLE =>
294 ram_enable_cntr <= ram_enable_cntr + 1;
295 new_rates_busy <= '1';
296 if (ram_enable_cntr = 0) then
297 ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
298 FTU_control_State <= CONFIG_ENABLE;
299 elsif (ram_enable_cntr > 0 and ram_enable_cntr < NO_OF_ENABLE + 1) then
300 ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
301 enable_array_sig(ram_enable_cntr - 1) <= ram_dob;
302 enables_ready <= '1';
303 FTU_control_State <= CONFIG_ENABLE;
304 else
305 ram_adb_sig <= (others => '0');
306 ram_enable_cntr <= 0;
307 new_enables_in_RAM <= '0';
308 ram_enb_sig <= '0';
309 cntr_reset_sig <= '1';
310 new_rates_busy <= '0';
311 enables_ready <= '0';
312 FTU_control_State <= RUNNING;
313 end if;
314
315 when CONFIG_DAC =>
316 new_rates_busy <= '1';
317 ram_dac_cntr <= ram_dac_cntr + 1;
318 if (ram_dac_cntr = 0) then
319 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);
320 FTU_control_State <= CONFIG_DAC;
321 elsif (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then
322 dac_array_sig(ram_dac_cntr - 1) <= conv_integer(unsigned(ram_dob(11 downto 0)));
323 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);
324 FTU_control_State <= CONFIG_DAC;
325 elsif (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED + 1)) then
326 dac_array_sig(ram_dac_cntr - 1 + NO_OF_DAC_NOT_USED) <= conv_integer(unsigned(ram_dob(11 downto 0)));
327 ram_adb_sig <= (others => '0');
328 FTU_control_State <= CONFIG_DAC;
329 DACs_ready <= '1';
330 else
331 ram_adb_sig <= (others => '0');
332 ram_enb_sig <= '0';
333 config_start_sig <= '1';
334 ram_dac_cntr <= 0;
335 DACs_ready <= '0';
336 FTU_control_State <= CONFIG_DAC_WAIT;
337 end if;
338
339 when CONFIG_DAC_WAIT =>
340 if (config_ready = '1') then
341 new_DACs_in_RAM <= '0';
342 cntr_reset_sig <= '1';
343 new_rates_busy <= '0';
344 config_start_sig <= '0';
345 FTU_control_State <= RUNNING;
346 elsif (config_ready = '0' and config_started = '1') then
347 new_rates_busy <= '1';
348 config_start_sig <= '0';
349 FTU_control_State <= CONFIG_DAC_WAIT;
350 else
351 new_rates_busy <= '1';
352 config_start_sig <= '1';
353 FTU_control_State <= CONFIG_DAC_WAIT;
354 end if;
355
356 when WRITE_RATES => -- write trigger/patch rates to RAM B and overflow register to RAM A
357 new_rates_busy <= '1';
358 ram_counter_cntr <= ram_counter_cntr + 1;
359 if (ram_counter_cntr < NO_OF_COUNTER) then
360 ram_enb_sig <= '1';
361 ram_web_sig <= "1";
362 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr), RAM_ADDR_WIDTH_B);
363 ram_dib_sig <= conv_std_logic_vector(rate_array_sig(ram_counter_cntr), 16);
364 FTU_control_State <= WRITE_RATES;
365 elsif (ram_counter_cntr = NO_Of_COUNTER) then
366 ram_dib_sig <= (others => '0');
367 ram_adb_sig <= (others => '0');
368 ram_enb_sig <= '0';
369 ram_web_sig <= "0";
370 ram_ena_sig <= '1';
371 ram_wea_sig <= "1";
372 ram_ada_sig <= conv_std_logic_vector(NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1, RAM_ADDR_WIDTH_A);
373 ram_dia_sig <= overflow_array;
374 FTU_control_State <= WRITE_RATES;
375 else
376 ram_ena_sig <= '0';
377 ram_wea_sig <= "0";
378 ram_counter_cntr <= 0;
379 new_rates_busy <= '0';
380 FTU_control_State <= RUNNING;
381 end if;
382
383 when WRITE_DAC => -- write new DAC values from RS485 to RAM
384 ram_dac_cntr <= ram_dac_cntr + 1;
385 if (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)) then
386 ram_enb_sig <= '1';
387 ram_web_sig <= "1";
388 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr), RAM_ADDR_WIDTH_B);
389 ram_dib_sig <= conv_std_logic_vector(dac_array_rs485_out(ram_dac_cntr), 16);
390 FTU_control_State <= WRITE_DAC;
391 elsif (ram_dac_cntr = (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)) then
392 ram_enb_sig <= '1';
393 ram_web_sig <= "1";
394 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr), RAM_ADDR_WIDTH_B);
395 ram_dib_sig <= conv_std_logic_vector(dac_array_rs485_out(ram_dac_cntr + NO_OF_DAC_NOT_USED), 16);
396 FTU_control_State <= WRITE_DAC;
397 else
398 ram_enb_sig <= '0';
399 ram_web_sig <= "0";
400 new_DACs_in_RAM <= '1';
401 ram_dib_sig <= (others => '0');
402 ram_adb_sig <= (others => '0');
403 ram_dac_cntr <= 0;
404 FTU_control_State <= RUNNING;
405 end if;
406
407 when WRITE_ENABLE => -- write new enable patterns from RS485 to RAM
408 ram_enable_cntr <= ram_enable_cntr + 1;
409 if (ram_enable_cntr < NO_OF_ENABLE) then
410 ram_enb_sig <= '1';
411 ram_web_sig <= "1";
412 ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr, RAM_ADDR_WIDTH_B);
413 ram_dib_sig <= enable_array_rs485_out(ram_enable_cntr);
414 else
415 ram_enb_sig <= '0';
416 ram_web_sig <= "0";
417 new_enables_in_RAM <= '1';
418 ram_dib_sig <= (others => '0');
419 ram_adb_sig <= (others => '0');
420 ram_enable_cntr <= 0;
421 FTU_control_State <= RUNNING;
422 end if;
423
424 when WRITE_PRESCALING => -- write new prescaling from RS485 to RAM
425 wait_cntr <= wait_cntr + 1;
426 if (wait_cntr = 0) then
427 ram_ena_sig <= '1';
428 ram_wea_sig <= "1";
429 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A);
430 ram_dia_sig <= prescaling_rs485_out;
431 else
432 ram_ena_sig <= '0';
433 ram_wea_sig <= "0";
434 new_prescaling_in_RAM <= '1';
435 ram_dia_sig <= (others => '0');
436 ram_ada_sig <= (others => '0');
437 wait_cntr <= 0;
438 FTU_control_State <= RUNNING;
439 end if;
440
441 when READOUT_RATES => -- read most recent rate values from RAM and send them to RS485 module
442 ram_counter_cntr <= ram_counter_cntr + 1;
443 if (ram_counter_cntr = 0) then
444 ram_enb_sig <= '1';
445 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr + 1), RAM_ADDR_WIDTH_B);
446 FTU_control_State <= READOUT_RATES;
447 elsif (ram_counter_cntr < NO_OF_COUNTER) then
448 ram_ena_sig <= '1';
449 ram_ada_sig <= conv_std_logic_vector(((NO_OF_ENABLE + NO_OF_COUNTER + NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1), RAM_ADDR_WIDTH_A);
450 ram_enb_sig <= '1';
451 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr + 1), RAM_ADDR_WIDTH_B);
452 rate_array_rs485(ram_counter_cntr - 1) <= conv_integer(unsigned(ram_dob));
453 FTU_control_State <= READOUT_RATES;
454 elsif (ram_counter_cntr = NO_Of_COUNTER) then
455 ram_enb_sig <= '0';
456 ram_adb_sig <= (others => '0');
457 rate_array_rs485(ram_counter_cntr - 1) <= conv_integer(unsigned(ram_dob));
458 ram_ena_sig <= '1';
459 ram_ada_sig <= conv_std_logic_vector(((NO_OF_ENABLE + NO_OF_COUNTER + NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1), RAM_ADDR_WIDTH_A);
460 FTU_control_State <= READOUT_RATES;
461 elsif (ram_counter_cntr = NO_Of_COUNTER + 1) then
462 ram_enb_sig <= '0';
463 ram_adb_sig <= (others => '0');
464 ram_ena_sig <= '0';
465 ram_ada_sig <= (others => '0');
466 overflow_array_rs485_in <= ram_doa;
467 rates_ready <= '1';
468 FTU_control_State <= READOUT_RATES;
469 else
470 ram_enb_sig <= '0';
471 ram_adb_sig <= (others => '0');
472 ram_ena_sig <= '0';
473 ram_ada_sig <= (others => '0');
474 ram_counter_cntr <= 0;
475 rates_ready <= '0';
476 FTU_control_State <= RUNNING;
477 end if;
478
479 when READOUT_DAC => -- read most recent DAC values from RAM and send them to RS485 module
480 ram_dac_cntr <= ram_dac_cntr + 1;
481 if (ram_dac_cntr = 0) then
482 ram_enb_sig <= '1';
483 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);
484 FTU_control_State <= READOUT_DAC;
485 elsif (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then
486 ram_enb_sig <= '1';
487 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);
488 dac_array_sig(ram_dac_cntr - 1) <= conv_integer(unsigned(ram_dob(11 downto 0)));
489 FTU_control_State <= READOUT_DAC;
490 elsif (ram_dac_cntr = (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then
491 ram_enb_sig <= '0';
492 ram_adb_sig <= (others => '0');
493 dac_array_sig(ram_dac_cntr + NO_OF_DAC_NOT_USED - 1) <= conv_integer(unsigned(ram_dob(11 downto 0)));
494 DACs_ready <= '1';
495 FTU_control_State <= READOUT_DAC;
496 else
497 ram_enb_sig <= '0';
498 ram_adb_sig <= (others => '0');
499 DACs_ready <= '0';
500 ram_dac_cntr <= 0;
501 FTU_control_State <= RUNNING;
502 end if;
503
504 when READOUT_ENABLE => -- read most recent enable patterns from RAM and send them to RS485 module
505 ram_enable_cntr <= ram_enable_cntr + 1;
506 if (ram_enable_cntr = 0) then
507 ram_enb_sig <= '1';
508 ram_adb_sig <= conv_std_logic_vector((ram_enable_cntr + 1), RAM_ADDR_WIDTH_B);
509 FTU_control_State <= READOUT_ENABLE;
510 elsif (ram_enable_cntr < NO_OF_ENABLE) then
511 ram_enb_sig <= '1';
512 ram_adb_sig <= conv_std_logic_vector((ram_enable_cntr + 1), RAM_ADDR_WIDTH_B);
513 enable_array_sig(ram_enable_cntr - 1) <= ram_dob;
514 FTU_control_State <= READOUT_ENABLE;
515 elsif (ram_enable_cntr = NO_OF_ENABLE) then
516 ram_enb_sig <= '0';
517 ram_adb_sig <= (others => '0');
518 enable_array_sig(ram_enable_cntr - 1) <= ram_dob;
519 enables_ready <= '1';
520 FTU_control_State <= READOUT_ENABLE;
521 else
522 ram_enb_sig <= '0';
523 ram_adb_sig <= (others => '0');
524 enables_ready <= '0';
525 ram_enable_cntr <= 0;
526 FTU_control_State <= RUNNING;
527 end if;
528
529 when READOUT_PRESCALING => -- read most recent prescaling value from RAM and send it to RS485 module
530 wait_cntr <= wait_cntr + 1;
531 if (wait_cntr = 0) then
532 ram_ena_sig <= '1';
533 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 1, RAM_ADDR_WIDTH_A);
534 FTU_control_State <= READOUT_PRESCALING;
535 elsif (wait_cntr = 1) then
536 ram_ena_sig <= '1';
537 ram_ada_sig <= (others => '0');
538 prescaling_sig <= ram_doa;
539 FTU_control_State <= READOUT_PRESCALING;
540 elsif (wait_cntr = 2) then
541 ram_ena_sig <= '0';
542 ram_ada_sig <= (others => '0');
543 overflow_array_rs485_in <= ram_doa;
544 prescaling_ready <= '1';
545 FTU_control_State <= READOUT_PRESCALING;
546 else
547 ram_ena_sig <= '0';
548 ram_ada_sig <= (others => '0');
549 prescaling_ready <= '0';
550 wait_cntr <= 0;
551 FTU_control_State <= RUNNING;
552 end if;
553
554 when DO_PING_PONG => -- just answer to FTM
555 wait_cntr <= wait_cntr + 1;
556 if (wait_cntr = 0) then
557 ping_pong_ready <= '1';
558 FTU_control_State <= DO_PING_PONG;
559 else
560 ping_pong_ready <= '0';
561 wait_cntr <= 0;
562 FTU_control_State <= RUNNING;
563 end if;
564
565 end case;
566 end if;
567 end process FTU_control_FSM;
568
569 detect_new_rates: process(new_rates, new_rates_busy)
570 begin
571 if(new_rates_busy = '1') then
572 new_rates_sig <= '0';
573 elsif rising_edge(new_rates) then
574 new_rates_sig <= '1';
575 end if;
576 end process detect_new_rates;
577
578 reset <= reset_sig;
579
580 config_start <= config_start_sig;
581 dac_array <= dac_array_sig;
582
583 enable_array <= enable_array_sig;
584 prescaling <= prescaling_sig;
585
586 rate_array_sig <= rate_array;
587 cntr_reset <= cntr_reset_sig;
588
589 ram_ena <= ram_ena_sig;
590 ram_enb <= ram_enb_sig;
591 ram_wea <= ram_wea_sig;
592 ram_web <= ram_web_sig;
593 ram_ada <= ram_ada_sig;
594 ram_adb <= ram_adb_sig;
595 ram_dia <= ram_dia_sig;
596 ram_dib <= ram_dib_sig;
597
598end Behavioral;
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