source: firmware/FTU/FTU_control.vhd@ 10047

Last change on this file since 10047 was 10037, checked in by weitzel, 14 years ago
FTU counter changed from 16 to 30 bit
File size: 30.0 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 08/06/2010
6-- Design Name:
7-- Module Name: FTU_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Control FSM of FACT FTU board
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Revision 0.02 - change-over to 64 byte RAM, 19.10.2010, Q. Weitzel
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21
22library IEEE;
23use IEEE.STD_LOGIC_1164.ALL;
24use IEEE.STD_LOGIC_ARITH.ALL;
25use IEEE.STD_LOGIC_UNSIGNED.ALL;
26
27library ftu_definitions;
28USE ftu_definitions.ftu_array_types.all;
29USE ftu_definitions.ftu_constants.all;
30
31---- Uncomment the following library declaration if instantiating
32---- any Xilinx primitives in this code.
33--library UNISIM;
34--use UNISIM.VComponents.all;
35
36entity FTU_control is
37 port(
38 clk_50MHz : IN std_logic;
39 clk_ready : IN std_logic; -- from DCM
40 config_started : IN std_logic; -- from DAC/SPI
41 config_ready : IN std_logic; -- from DAC/SPI
42 ram_doa : IN STD_LOGIC_VECTOR(7 downto 0);
43 ram_dob : IN STD_LOGIC_VECTOR(15 downto 0);
44 rate_array : IN rate_array_type; -- from counters
45 overflow_array : IN STD_LOGIC_VECTOR(7 downto 0); -- from counters
46 new_rates : IN std_logic; -- from counters
47 new_DACs : IN std_logic; -- from RS485 module
48 new_enables : IN std_logic; -- from RS485 module
49 new_prescaling : IN std_logic; -- from RS485 module
50 read_rates : IN std_logic; -- from RS485 module
51 read_DACs : IN std_logic; -- from RS485 module
52 read_enables : IN std_logic; -- from RS485 module
53 read_prescaling : IN std_logic; -- from RS485 module
54 ping_pong : IN std_logic; -- from RS485 module
55 dac_array_rs485_out : IN dac_array_type; -- from RS485 module
56 enable_array_rs485_out : IN enable_array_type; -- from RS485 module
57 prescaling_rs485_out : IN STD_LOGIC_VECTOR(7 downto 0); -- from RS485 module
58 dna_ready : IN std_logic; -- from FTU_dna_gen
59 reset : OUT std_logic;
60 config_start : OUT std_logic;
61 ram_ena : OUT std_logic;
62 ram_enb : OUT std_logic;
63 ram_wea : OUT STD_LOGIC_VECTOR(0 downto 0);
64 ram_web : OUT STD_LOGIC_VECTOR(0 downto 0);
65 ram_ada : OUT STD_LOGIC_VECTOR(5 downto 0);
66 ram_adb : OUT STD_LOGIC_VECTOR(4 downto 0);
67 ram_dia : OUT STD_LOGIC_VECTOR(7 downto 0);
68 ram_dib : OUT STD_LOGIC_VECTOR(15 downto 0);
69 rate_array_rs485 : OUT rate_array_type := (0,0,0,0,0); -- to RS485 module
70 overflow_array_rs485_in : OUT STD_LOGIC_VECTOR(7 downto 0) := "00000000"; -- to RS485 module
71 rates_ready : OUT std_logic := '0'; -- to RS485 module
72 DACs_ready : OUT std_logic := '0'; -- to RS485 module
73 enables_ready : OUT std_logic := '0'; -- to RS485 module
74 prescaling_ready : OUT std_logic := '0'; -- to RS485 module
75 ping_pong_ready : OUT std_logic := '0'; -- to RS485 module
76 dac_array : OUT dac_array_type;
77 enable_array : OUT enable_array_type;
78 cntr_reset : OUT STD_LOGIC;
79 prescaling : OUT STD_LOGIC_VECTOR(7 downto 0);
80 dna_start : OUT std_logic := '0' -- to FTU_dna_gen
81 );
82end FTU_control;
83
84architecture Behavioral of FTU_control is
85
86 signal new_rates_sr : std_logic_vector(1 downto 0) := (others => '0');
87
88 signal reset_sig : STD_LOGIC := '0'; --initialize reset to 0 at power up
89
90 --DAC/SPI interface, default DACs come from RAM during INIT
91 signal config_start_sig : STD_LOGIC := '0';
92 signal dac_array_sig : dac_array_type := (0,0,0,0,0,0,0,0);
93
94 --enable signals for pixels in trigger, default values come from RAM during INIT
95 signal enable_array_sig : enable_array_type := ("0000000000000000", --patch A
96 "0000000000000000", --patch B
97 "0000000000000000", --patch C
98 "0000000000000000");--patch D
99
100 signal rate_array_sig : rate_array_type; -- initialized in FTU_top
101 signal cntr_reset_sig : STD_LOGIC := '0';
102 signal prescaling_sig : STD_LOGIC_VECTOR(7 downto 0) := "00011101"; -- 29
103
104 signal ram_ena_sig : STD_LOGIC := '0'; -- RAM enable for port A
105 signal ram_enb_sig : STD_LOGIC := '0'; -- RAM enable for port B
106 signal ram_wea_sig : STD_LOGIC_VECTOR(0 downto 0) := "0"; -- RAM write enable for port A
107 signal ram_web_sig : STD_LOGIC_VECTOR(0 downto 0) := "0"; -- RAM write enable for port B
108 signal ram_ada_sig : STD_LOGIC_VECTOR(5 downto 0) := (others => '0'); --RAM port A address
109 signal ram_adb_sig : STD_LOGIC_VECTOR(4 downto 0) := (others => '0'); --RAM port B address
110 signal ram_dia_sig : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); --RAM data in A
111 signal ram_dib_sig : STD_LOGIC_VECTOR(15 downto 0) := (others => '0'); --RAM data in B
112
113 --counter to loop through RAM
114 signal ram_ada_cntr : INTEGER range 0 to 2**RAM_ADDR_WIDTH_A := 0;
115 signal ram_dac_cntr : INTEGER range 0 to (NO_OF_DAC - NO_OF_DAC_NOT_USED + 2) := 0;
116 signal ram_enable_cntr : INTEGER range 0 to (NO_OF_ENABLE + 1) := 0;
117 signal ram_counter_cntr : INTEGER range 0 to (NO_OF_COUNTER*RAM_CEF + 2) := 0; --includes overflow register
118
119 signal wait_cntr : INTEGER range 0 to 2**RAM_ADDR_WIDTH_A := 0;
120
121 signal new_rates_sig : STD_LOGIC := '0';
122 signal new_rates_busy : STD_LOGIC := '1'; -- veto the writing of new rates until in RUNNING
123
124 signal new_DACs_in_RAM : STD_LOGIC := '0';
125 signal new_enables_in_RAM : STD_LOGIC := '0';
126 signal new_prescaling_in_RAM : STD_LOGIC := '0';
127
128 signal ram_buffer_sig : STD_LOGIC_VECTOR(29 downto 0) := (others => '0');
129
130 type FTU_control_StateType is (IDLE, INIT_RAM, INIT_DNA, RUNNING,
131 CONFIG_ENABLE, CONFIG_DAC, CONFIG_DAC_WAIT, CONFIG_COUNTER,
132 WRITE_RATES, WRITE_DAC, WRITE_ENABLE, WRITE_PRESCALING,
133 READOUT_RATES, READOUT_DAC, READOUT_ENABLE, READOUT_PRESCALING,
134 DO_PING_PONG);
135 signal FTU_control_State : FTU_control_StateType;
136
137begin
138
139 --FTU control finite state machine
140
141 FTU_control_FSM: process (clk_50MHz)
142
143 begin
144
145 reset_sig <= '0';
146
147 if Rising_edge(clk_50MHz) then
148
149 case FTU_control_State is
150
151 when IDLE => -- wait for DCMs to lock
152 if (clk_ready = '1') then
153 FTU_control_State <= INIT_DNA;
154 else
155 FTU_control_State <= IDLE;
156 end if;
157
158 when INIT_DNA => -- determine FPGA DNA
159 if (dna_ready = '1') then
160 FTU_control_State <= INIT_RAM;
161 dna_start <= '0';
162 else
163 dna_start <= '1';
164 FTU_control_State <= INIT_DNA;
165 end if;
166
167 when INIT_RAM => -- load default config data to RAM, see also ftu_definitions.vhd for more info
168 ram_ena_sig <= '1';
169 ram_wea_sig <= "1";
170 ram_ada_cntr <= ram_ada_cntr + 1;
171 ram_ada_sig <= conv_std_logic_vector(ram_ada_cntr, RAM_ADDR_WIDTH_A);
172 if (ram_ada_cntr < NO_OF_ENABLE*RAM_ADDR_RATIO) then -- default enables
173 if (ram_ada_cntr mod 2 = 0) then
174 ram_dia_sig <= DEFAULT_ENABLE(ram_ada_cntr / 2)(7 downto 0);
175 else
176 ram_dia_sig <= DEFAULT_ENABLE(ram_ada_cntr / 2)(15 downto 8);
177 end if;
178 FTU_control_State <= INIT_RAM;
179 elsif (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF)) then -- default counter values
180 ram_dia_sig <= (others => '0');
181 FTU_control_State <= INIT_RAM;
182 elsif (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO)) then -- default DACs
183 if (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)*RAM_ADDR_RATIO)) then
184 if (ram_ada_cntr mod 2 = 0) then
185 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF)) / 2),16)(7 downto 0);
186 else
187 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF)) / 2),16)(15 downto 8);
188 end if;
189 else
190 if (ram_ada_cntr mod 2 = 0) then
191 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC(((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF)) / 2) + NO_OF_DAC_NOT_USED),16)(7 downto 0);
192 else
193 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC(((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF)) / 2) + NO_OF_DAC_NOT_USED),16)(15 downto 8);
194 end if;
195 end if;
196 FTU_control_State <= INIT_RAM;
197 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO)) then -- default prescaling
198 ram_dia_sig <= conv_std_logic_vector(DEFAULT_PRESCALING,8);
199 FTU_control_State <= INIT_RAM;
200 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 1) then -- default overflow register
201 ram_dia_sig <= (others => '0');
202 FTU_control_State <= INIT_RAM;
203 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 2) then -- default CRC errors
204 ram_dia_sig <= (others => '0');
205 FTU_control_State <= INIT_RAM;
206 elsif (ram_ada_cntr < 2**RAM_ADDR_WIDTH_A) then -- empty RAM cells
207 ram_dia_sig <= (others => '0');
208 FTU_control_State <= INIT_RAM;
209 else
210 ram_dia_sig <= (others => '0');
211 ram_ada_cntr <= 0;
212 ram_ada_sig <= (others => '0');
213 ram_ena_sig <= '0';
214 ram_wea_sig <= "0";
215 new_DACs_in_RAM <= '1';
216 new_enables_in_RAM <= '1';
217 new_prescaling_in_RAM <= '1';
218 cntr_reset_sig <= '1';
219 new_rates_busy <= '0';
220 FTU_control_State <= RUNNING;
221 end if;
222
223 when RUNNING => -- count triggers and react to commands from FTM
224 cntr_reset_sig <= '0';
225 config_start_sig <= '0';
226 if (new_rates_sig = '1') then -- counters have finished a period
227 FTU_control_State <= WRITE_RATES;
228 else -- update FTU settings if necessary
229 if (new_DACs_in_RAM = '1') then
230 ram_enb_sig <= '1';
231 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF), RAM_ADDR_WIDTH_B);
232 FTU_control_State <= CONFIG_DAC;
233 elsif (new_DACs_in_RAM = '0' and new_enables_in_RAM = '1') then
234 ram_enb_sig <= '1';
235 ram_adb_sig <= conv_std_logic_vector(0, RAM_ADDR_WIDTH_B);
236 FTU_control_State <= CONFIG_ENABLE;
237 elsif (new_DACs_in_RAM = '0' and new_enables_in_RAM = '0' and new_prescaling_in_RAM = '1') then
238 ram_ena_sig <= '1';
239 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A);
240 FTU_control_State <= CONFIG_COUNTER;
241 else -- nothing to be updated, check new commands from RS485
242 if (new_DACs = '1') then
243 FTU_control_State <= WRITE_DAC;
244 elsif (new_DACs = '0' and new_enables = '1') then
245 FTU_control_State <= WRITE_ENABLE;
246 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '1') then
247 FTU_control_State <= WRITE_PRESCALING;
248 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and
249 read_rates = '1') then
250 ram_enb_sig <= '1';
251 ram_adb_sig <= conv_std_logic_vector(NO_OF_ENABLE, RAM_ADDR_WIDTH_B);
252 FTU_control_State <= READOUT_RATES;
253 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and
254 read_rates = '0' and read_DACs = '1') then
255 ram_enb_sig <= '1';
256 ram_adb_sig <= conv_std_logic_vector(NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF, RAM_ADDR_WIDTH_B);
257 FTU_control_State <= READOUT_DAC;
258 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and
259 read_rates = '0' and read_DACs = '0' and read_enables = '1') then
260 ram_enb_sig <= '1';
261 ram_adb_sig <= conv_std_logic_vector(0, RAM_ADDR_WIDTH_B);
262 FTU_control_State <= READOUT_ENABLE;
263 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and
264 read_rates = '0' and read_DACs = '0' and read_enables = '0' and read_prescaling = '1') then
265 ram_ena_sig <= '1';
266 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A);
267 FTU_control_State <= READOUT_PRESCALING;
268 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and
269 read_rates = '0' and read_DACs = '0' and read_enables = '0' and read_prescaling = '0' and
270 ping_pong = '1') then
271 FTU_control_State <= DO_PING_PONG;
272 else
273 FTU_control_State <= RUNNING; --no commands from RS485 -> stay running
274 end if;
275 end if;
276 end if;
277
278 when CONFIG_COUNTER =>
279 wait_cntr <= wait_cntr + 1;
280 new_rates_busy <= '1';
281 if (wait_cntr = 0) then
282 FTU_control_State <= CONFIG_COUNTER;
283 elsif (wait_cntr = 1) then
284 prescaling_sig <= ram_doa;
285 FTU_control_State <= CONFIG_COUNTER;
286 prescaling_ready <= '1';
287 else
288 cntr_reset_sig <= '1';
289 ram_ada_sig <= (others => '0');
290 wait_cntr <= 0;
291 new_prescaling_in_RAM <= '0';
292 ram_ena_sig <= '0';
293 new_rates_busy <= '0';
294 prescaling_ready <= '0';
295 FTU_control_State <= RUNNING;
296 end if;
297
298 when CONFIG_ENABLE =>
299 ram_enable_cntr <= ram_enable_cntr + 1;
300 new_rates_busy <= '1';
301 if (ram_enable_cntr = 0) then
302 ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
303 FTU_control_State <= CONFIG_ENABLE;
304 elsif (ram_enable_cntr > 0 and ram_enable_cntr < NO_OF_ENABLE + 1) then
305 ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
306 enable_array_sig(ram_enable_cntr - 1) <= ram_dob;
307 enables_ready <= '1';
308 FTU_control_State <= CONFIG_ENABLE;
309 else
310 ram_adb_sig <= (others => '0');
311 ram_enable_cntr <= 0;
312 new_enables_in_RAM <= '0';
313 ram_enb_sig <= '0';
314 cntr_reset_sig <= '1';
315 new_rates_busy <= '0';
316 enables_ready <= '0';
317 FTU_control_State <= RUNNING;
318 end if;
319
320 when CONFIG_DAC =>
321 new_rates_busy <= '1';
322 ram_dac_cntr <= ram_dac_cntr + 1;
323 if (ram_dac_cntr = 0) then
324 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);
325 FTU_control_State <= CONFIG_DAC;
326 elsif (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then
327 dac_array_sig(ram_dac_cntr - 1) <= conv_integer(unsigned(ram_dob(11 downto 0)));
328 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);
329 FTU_control_State <= CONFIG_DAC;
330 elsif (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED + 1)) then
331 dac_array_sig(4) <= 0;
332 dac_array_sig(5) <= 0;
333 dac_array_sig(6) <= 0;
334 dac_array_sig(ram_dac_cntr - 1 + NO_OF_DAC_NOT_USED) <= conv_integer(unsigned(ram_dob(11 downto 0)));
335 ram_adb_sig <= (others => '0');
336 FTU_control_State <= CONFIG_DAC;
337 DACs_ready <= '1';
338 else
339 ram_adb_sig <= (others => '0');
340 ram_enb_sig <= '0';
341 config_start_sig <= '1';
342 ram_dac_cntr <= 0;
343 DACs_ready <= '0';
344 FTU_control_State <= CONFIG_DAC_WAIT;
345 end if;
346
347 when CONFIG_DAC_WAIT =>
348 if (config_ready = '1') then
349 new_DACs_in_RAM <= '0';
350 cntr_reset_sig <= '1';
351 new_rates_busy <= '0';
352 config_start_sig <= '0';
353 FTU_control_State <= RUNNING;
354 elsif (config_ready = '0' and config_started = '1') then
355 new_rates_busy <= '1';
356 config_start_sig <= '0';
357 FTU_control_State <= CONFIG_DAC_WAIT;
358 else
359 new_rates_busy <= '1';
360 config_start_sig <= '1';
361 FTU_control_State <= CONFIG_DAC_WAIT;
362 end if;
363
364 when WRITE_RATES => -- write trigger/patch rates to RAM B and overflow register to RAM A
365 new_rates_busy <= '1';
366 ram_counter_cntr <= ram_counter_cntr + 1;
367 if (ram_counter_cntr < NO_OF_COUNTER*RAM_CEF) then
368 ram_enb_sig <= '1';
369 ram_web_sig <= "1";
370 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr), RAM_ADDR_WIDTH_B);
371 if (ram_counter_cntr mod 2 = 0) then
372 ram_dib_sig <= conv_std_logic_vector(rate_array_sig(ram_counter_cntr / 2), 32)(15 downto 0);
373 else
374 ram_dib_sig <= conv_std_logic_vector(rate_array_sig(ram_counter_cntr / 2), 32)(31 downto 16);
375 end if;
376 FTU_control_State <= WRITE_RATES;
377 elsif (ram_counter_cntr = NO_Of_COUNTER*RAM_CEF) then
378 ram_dib_sig <= (others => '0');
379 ram_adb_sig <= (others => '0');
380 ram_enb_sig <= '0';
381 ram_web_sig <= "0";
382 ram_ena_sig <= '1';
383 ram_wea_sig <= "1";
384 ram_ada_sig <= conv_std_logic_vector(NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1, RAM_ADDR_WIDTH_A);
385 ram_dia_sig <= overflow_array;
386 FTU_control_State <= WRITE_RATES;
387 else
388 ram_ena_sig <= '0';
389 ram_wea_sig <= "0";
390 ram_counter_cntr <= 0;
391 new_rates_busy <= '0';
392 FTU_control_State <= RUNNING;
393 end if;
394
395 when WRITE_DAC => -- write new DAC values from RS485 to RAM
396 ram_dac_cntr <= ram_dac_cntr + 1;
397 if (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)) then
398 ram_enb_sig <= '1';
399 ram_web_sig <= "1";
400 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + ram_dac_cntr), RAM_ADDR_WIDTH_B);
401 ram_dib_sig <= conv_std_logic_vector(dac_array_rs485_out(ram_dac_cntr), 16);
402 FTU_control_State <= WRITE_DAC;
403 elsif (ram_dac_cntr = (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)) then
404 ram_enb_sig <= '1';
405 ram_web_sig <= "1";
406 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + ram_dac_cntr), RAM_ADDR_WIDTH_B);
407 ram_dib_sig <= conv_std_logic_vector(dac_array_rs485_out(ram_dac_cntr + NO_OF_DAC_NOT_USED), 16);
408 FTU_control_State <= WRITE_DAC;
409 else
410 ram_enb_sig <= '0';
411 ram_web_sig <= "0";
412 new_DACs_in_RAM <= '1';
413 ram_dib_sig <= (others => '0');
414 ram_adb_sig <= (others => '0');
415 ram_dac_cntr <= 0;
416 FTU_control_State <= RUNNING;
417 end if;
418
419 when WRITE_ENABLE => -- write new enable patterns from RS485 to RAM
420 ram_enable_cntr <= ram_enable_cntr + 1;
421 if (ram_enable_cntr < NO_OF_ENABLE) then
422 ram_enb_sig <= '1';
423 ram_web_sig <= "1";
424 ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr, RAM_ADDR_WIDTH_B);
425 ram_dib_sig <= enable_array_rs485_out(ram_enable_cntr);
426 else
427 ram_enb_sig <= '0';
428 ram_web_sig <= "0";
429 new_enables_in_RAM <= '1';
430 ram_dib_sig <= (others => '0');
431 ram_adb_sig <= (others => '0');
432 ram_enable_cntr <= 0;
433 FTU_control_State <= RUNNING;
434 end if;
435
436 when WRITE_PRESCALING => -- write new prescaling from RS485 to RAM
437 wait_cntr <= wait_cntr + 1;
438 if (wait_cntr = 0) then
439 ram_ena_sig <= '1';
440 ram_wea_sig <= "1";
441 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A);
442 ram_dia_sig <= prescaling_rs485_out;
443 else
444 ram_ena_sig <= '0';
445 ram_wea_sig <= "0";
446 new_prescaling_in_RAM <= '1';
447 ram_dia_sig <= (others => '0');
448 ram_ada_sig <= (others => '0');
449 wait_cntr <= 0;
450 FTU_control_State <= RUNNING;
451 end if;
452
453 when READOUT_RATES => -- read most recent rate values from RAM and send them to RS485 module
454 ram_counter_cntr <= ram_counter_cntr + 1;
455 if (ram_counter_cntr = 0) then
456 ram_enb_sig <= '1';
457 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr + 1), RAM_ADDR_WIDTH_B);
458 FTU_control_State <= READOUT_RATES;
459 elsif (ram_counter_cntr < 3) then
460 ram_ena_sig <= '1';
461 ram_ada_sig <= conv_std_logic_vector(((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1), RAM_ADDR_WIDTH_A);
462 ram_enb_sig <= '1';
463 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr + 1), RAM_ADDR_WIDTH_B);
464 if (ram_counter_cntr = 1) then
465 ram_buffer_sig(15 downto 0) <= ram_dob;
466 else
467 ram_buffer_sig(29 downto 16) <= ram_dob(13 downto 0);
468 end if;
469 FTU_control_State <= READOUT_RATES;
470 elsif (ram_counter_cntr < NO_OF_COUNTER*RAM_CEF) then
471 ram_ena_sig <= '1';
472 ram_ada_sig <= conv_std_logic_vector(((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1), RAM_ADDR_WIDTH_A);
473 ram_enb_sig <= '1';
474 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr + 1), RAM_ADDR_WIDTH_B);
475 if (ram_counter_cntr mod 2 = 1) then
476 ram_buffer_sig(15 downto 0) <= ram_dob;
477 rate_array_rs485((ram_counter_cntr / 2) - 1) <= conv_integer(unsigned(ram_buffer_sig));
478 else
479 ram_buffer_sig(29 downto 16) <= ram_dob(13 downto 0);
480 end if;
481 FTU_control_State <= READOUT_RATES;
482 elsif (ram_counter_cntr = NO_Of_COUNTER*RAM_CEF) then
483 ram_enb_sig <= '0';
484 ram_adb_sig <= (others => '0');
485 ram_buffer_sig(29 downto 16) <= ram_dob(13 downto 0);
486 ram_ena_sig <= '1';
487 ram_ada_sig <= conv_std_logic_vector(((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1), RAM_ADDR_WIDTH_A);
488 FTU_control_State <= READOUT_RATES;
489 elsif (ram_counter_cntr = NO_Of_COUNTER*RAM_CEF + 1) then
490 rate_array_rs485((ram_counter_cntr / 2) - 1) <= conv_integer(unsigned(ram_buffer_sig));
491 ram_buffer_sig <= (others => '0');
492 ram_enb_sig <= '0';
493 ram_adb_sig <= (others => '0');
494 ram_ena_sig <= '0';
495 ram_ada_sig <= (others => '0');
496 overflow_array_rs485_in <= ram_doa;
497 rates_ready <= '1';
498 FTU_control_State <= READOUT_RATES;
499 else
500 ram_enb_sig <= '0';
501 ram_adb_sig <= (others => '0');
502 ram_ena_sig <= '0';
503 ram_ada_sig <= (others => '0');
504 ram_counter_cntr <= 0;
505 rates_ready <= '0';
506 FTU_control_State <= RUNNING;
507 end if;
508
509 when READOUT_DAC => -- read most recent DAC values from RAM and send them to RS485 module
510 ram_dac_cntr <= ram_dac_cntr + 1;
511 if (ram_dac_cntr = 0) then
512 ram_enb_sig <= '1';
513 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);
514 FTU_control_State <= READOUT_DAC;
515 elsif (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then
516 ram_enb_sig <= '1';
517 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);
518 dac_array_sig(ram_dac_cntr - 1) <= conv_integer(unsigned(ram_dob(11 downto 0)));
519 FTU_control_State <= READOUT_DAC;
520 elsif (ram_dac_cntr = (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then
521 ram_enb_sig <= '0';
522 ram_adb_sig <= (others => '0');
523 dac_array_sig(ram_dac_cntr + NO_OF_DAC_NOT_USED - 1) <= conv_integer(unsigned(ram_dob(11 downto 0)));
524 DACs_ready <= '1';
525 FTU_control_State <= READOUT_DAC;
526 else
527 ram_enb_sig <= '0';
528 ram_adb_sig <= (others => '0');
529 DACs_ready <= '0';
530 ram_dac_cntr <= 0;
531 FTU_control_State <= RUNNING;
532 end if;
533
534 when READOUT_ENABLE => -- read most recent enable patterns from RAM and send them to RS485 module
535 ram_enable_cntr <= ram_enable_cntr + 1;
536 if (ram_enable_cntr = 0) then
537 ram_enb_sig <= '1';
538 ram_adb_sig <= conv_std_logic_vector((ram_enable_cntr + 1), RAM_ADDR_WIDTH_B);
539 FTU_control_State <= READOUT_ENABLE;
540 elsif (ram_enable_cntr < NO_OF_ENABLE) then
541 ram_enb_sig <= '1';
542 ram_adb_sig <= conv_std_logic_vector((ram_enable_cntr + 1), RAM_ADDR_WIDTH_B);
543 enable_array_sig(ram_enable_cntr - 1) <= ram_dob;
544 FTU_control_State <= READOUT_ENABLE;
545 elsif (ram_enable_cntr = NO_OF_ENABLE) then
546 ram_enb_sig <= '0';
547 ram_adb_sig <= (others => '0');
548 enable_array_sig(ram_enable_cntr - 1) <= ram_dob;
549 enables_ready <= '1';
550 FTU_control_State <= READOUT_ENABLE;
551 else
552 ram_enb_sig <= '0';
553 ram_adb_sig <= (others => '0');
554 enables_ready <= '0';
555 ram_enable_cntr <= 0;
556 FTU_control_State <= RUNNING;
557 end if;
558
559 when READOUT_PRESCALING => -- read most recent prescaling value from RAM and send it to RS485 module
560 wait_cntr <= wait_cntr + 1;
561 if (wait_cntr = 0) then
562 ram_ena_sig <= '1';
563 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 1, RAM_ADDR_WIDTH_A);
564 FTU_control_State <= READOUT_PRESCALING;
565 elsif (wait_cntr = 1) then
566 ram_ena_sig <= '1';
567 ram_ada_sig <= (others => '0');
568 prescaling_sig <= ram_doa;
569 FTU_control_State <= READOUT_PRESCALING;
570 elsif (wait_cntr = 2) then
571 ram_ena_sig <= '0';
572 ram_ada_sig <= (others => '0');
573 overflow_array_rs485_in <= ram_doa;
574 prescaling_ready <= '1';
575 FTU_control_State <= READOUT_PRESCALING;
576 else
577 ram_ena_sig <= '0';
578 ram_ada_sig <= (others => '0');
579 prescaling_ready <= '0';
580 wait_cntr <= 0;
581 FTU_control_State <= RUNNING;
582 end if;
583
584 when DO_PING_PONG => -- just answer to FTM
585 wait_cntr <= wait_cntr + 1;
586 if (wait_cntr = 0) then
587 ping_pong_ready <= '1';
588 FTU_control_State <= DO_PING_PONG;
589 else
590 ping_pong_ready <= '0';
591 wait_cntr <= 0;
592 FTU_control_State <= RUNNING;
593 end if;
594
595 end case;
596 end if;
597 end process FTU_control_FSM;
598
599 --detect_new_rates: process(new_rates, new_rates_busy)
600 --begin
601 --if(new_rates_busy = '1') then
602 --new_rates_sig <= '0';
603 --elsif rising_edge(new_rates) then
604 --new_rates_sig <= '1';
605 --end if;
606 --end process detect_new_rates;
607
608 detect_new_rates: process(clk_50MHz)
609 begin
610 if rising_edge(clk_50MHz) then
611 new_rates_sr <= new_rates_sr(new_rates_sr'left - 1 downto 0) & new_rates;
612 if(new_rates_busy = '1') then
613 new_rates_sig <= '0';
614 else
615 if (new_rates_sr(1 downto 0) = "01") then
616 new_rates_sig <= '1';
617 end if;
618 end if;
619 end if;
620 end process detect_new_rates;
621
622 reset <= reset_sig;
623
624 config_start <= config_start_sig;
625 dac_array <= dac_array_sig;
626
627 enable_array <= enable_array_sig;
628 prescaling <= prescaling_sig;
629
630 rate_array_sig <= rate_array;
631 cntr_reset <= cntr_reset_sig;
632
633 ram_ena <= ram_ena_sig;
634 ram_enb <= ram_enb_sig;
635 ram_wea <= ram_wea_sig;
636 ram_web <= ram_web_sig;
637 ram_ada <= ram_ada_sig;
638 ram_adb <= ram_adb_sig;
639 ram_dia <= ram_dia_sig;
640 ram_dib <= ram_dib_sig;
641
642end Behavioral;
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