source: firmware/FTU/FTU_control.vhd@ 18558

Last change on this file since 18558 was 10051, checked in by weitzel, 14 years ago
some code cleaning and more comments for FTU firmware
File size: 29.9 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 08/06/2010
6-- Design Name:
7-- Module Name: FTU_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Control FSM of FACT FTU board
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Revision 0.02 - change-over to 64 byte RAM, 19.10.2010, Q. Weitzel
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21
22library IEEE;
23use IEEE.STD_LOGIC_1164.ALL;
24use IEEE.STD_LOGIC_ARITH.ALL;
25use IEEE.STD_LOGIC_UNSIGNED.ALL;
26
27library ftu_definitions;
28USE ftu_definitions.ftu_array_types.all;
29USE ftu_definitions.ftu_constants.all;
30
31---- Uncomment the following library declaration if instantiating
32---- any Xilinx primitives in this code.
33--library UNISIM;
34--use UNISIM.VComponents.all;
35
36entity FTU_control is
37 port(
38 clk_50MHz : IN std_logic;
39 clk_ready : IN std_logic; -- from DCM
40 config_started : IN std_logic; -- from DAC/SPI
41 config_ready : IN std_logic; -- from DAC/SPI
42 ram_doa : IN STD_LOGIC_VECTOR(7 downto 0);
43 ram_dob : IN STD_LOGIC_VECTOR(15 downto 0);
44 rate_array : IN rate_array_type; -- from counters
45 overflow_array : IN STD_LOGIC_VECTOR(7 downto 0); -- from counters
46 new_rates : IN std_logic; -- from counters
47 new_DACs : IN std_logic; -- from RS485 module
48 new_enables : IN std_logic; -- from RS485 module
49 new_prescaling : IN std_logic; -- from RS485 module
50 read_rates : IN std_logic; -- from RS485 module
51 read_DACs : IN std_logic; -- from RS485 module
52 read_enables : IN std_logic; -- from RS485 module
53 read_prescaling : IN std_logic; -- from RS485 module
54 ping_pong : IN std_logic; -- from RS485 module
55 dac_array_rs485_out : IN dac_array_type; -- from RS485 module
56 enable_array_rs485_out : IN enable_array_type; -- from RS485 module
57 prescaling_rs485_out : IN STD_LOGIC_VECTOR(7 downto 0); -- from RS485 module
58 dna_ready : IN std_logic; -- from FTU_dna_gen
59 reset : OUT std_logic;
60 config_start : OUT std_logic;
61 ram_ena : OUT std_logic;
62 ram_enb : OUT std_logic;
63 ram_wea : OUT STD_LOGIC_VECTOR(0 downto 0);
64 ram_web : OUT STD_LOGIC_VECTOR(0 downto 0);
65 ram_ada : OUT STD_LOGIC_VECTOR(5 downto 0);
66 ram_adb : OUT STD_LOGIC_VECTOR(4 downto 0);
67 ram_dia : OUT STD_LOGIC_VECTOR(7 downto 0);
68 ram_dib : OUT STD_LOGIC_VECTOR(15 downto 0);
69 rate_array_rs485 : OUT rate_array_type := (0,0,0,0,0); -- to RS485 module
70 overflow_array_rs485_in : OUT STD_LOGIC_VECTOR(7 downto 0) := "00000000"; -- to RS485 module
71 rates_ready : OUT std_logic := '0'; -- to RS485 module
72 DACs_ready : OUT std_logic := '0'; -- to RS485 module
73 enables_ready : OUT std_logic := '0'; -- to RS485 module
74 prescaling_ready : OUT std_logic := '0'; -- to RS485 module
75 ping_pong_ready : OUT std_logic := '0'; -- to RS485 module
76 dac_array : OUT dac_array_type;
77 enable_array : OUT enable_array_type;
78 cntr_reset : OUT STD_LOGIC;
79 prescaling : OUT STD_LOGIC_VECTOR(7 downto 0);
80 dna_start : OUT std_logic := '0' -- to FTU_dna_gen
81 );
82end FTU_control;
83
84architecture Behavioral of FTU_control is
85
86 signal new_rates_sr : std_logic_vector(1 downto 0) := (others => '0');
87
88 signal reset_sig : STD_LOGIC := '0'; --initialize reset to 0 at power up
89
90 --DAC/SPI interface, default DACs come from RAM during INIT
91 signal config_start_sig : STD_LOGIC := '0';
92 signal dac_array_sig : dac_array_type := (0,0,0,0,0,0,0,0);
93
94 --enable signals for pixels in trigger, default values come from RAM during INIT
95 signal enable_array_sig : enable_array_type := ("0000000000000000", --patch A
96 "0000000000000000", --patch B
97 "0000000000000000", --patch C
98 "0000000000000000");--patch D
99
100 signal rate_array_sig : rate_array_type; -- initialized in FTU_top
101 signal cntr_reset_sig : STD_LOGIC := '0';
102 signal prescaling_sig : STD_LOGIC_VECTOR(7 downto 0) := "00011101"; -- 29
103
104 signal ram_ena_sig : STD_LOGIC := '0'; -- RAM enable for port A
105 signal ram_enb_sig : STD_LOGIC := '0'; -- RAM enable for port B
106 signal ram_wea_sig : STD_LOGIC_VECTOR(0 downto 0) := "0"; -- RAM write enable for port A
107 signal ram_web_sig : STD_LOGIC_VECTOR(0 downto 0) := "0"; -- RAM write enable for port B
108 signal ram_ada_sig : STD_LOGIC_VECTOR(5 downto 0) := (others => '0'); --RAM port A address
109 signal ram_adb_sig : STD_LOGIC_VECTOR(4 downto 0) := (others => '0'); --RAM port B address
110 signal ram_dia_sig : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); --RAM data in A
111 signal ram_dib_sig : STD_LOGIC_VECTOR(15 downto 0) := (others => '0'); --RAM data in B
112
113 --counter to loop through RAM
114 signal ram_ada_cntr : INTEGER range 0 to 2**RAM_ADDR_WIDTH_A := 0;
115 signal ram_dac_cntr : INTEGER range 0 to (NO_OF_DAC - NO_OF_DAC_NOT_USED + 2) := 0;
116 signal ram_enable_cntr : INTEGER range 0 to (NO_OF_ENABLE + 1) := 0;
117 signal ram_counter_cntr : INTEGER range 0 to (NO_OF_COUNTER*RAM_CEF + 2) := 0; --includes overflow register
118
119 signal wait_cntr : INTEGER range 0 to 2**RAM_ADDR_WIDTH_A := 0;
120
121 signal new_rates_sig : STD_LOGIC := '0';
122 signal new_rates_busy : STD_LOGIC := '1'; -- veto the writing of new rates until in RUNNING
123
124 signal new_DACs_in_RAM : STD_LOGIC := '0';
125 signal new_enables_in_RAM : STD_LOGIC := '0';
126 signal new_prescaling_in_RAM : STD_LOGIC := '0';
127
128 signal ram_buffer_sig : STD_LOGIC_VECTOR(29 downto 0) := (others => '0');
129
130 type FTU_control_StateType is (IDLE, INIT_RAM, INIT_DNA, RUNNING,
131 CONFIG_ENABLE, CONFIG_DAC, CONFIG_DAC_WAIT, CONFIG_COUNTER,
132 WRITE_RATES, WRITE_DAC, WRITE_ENABLE, WRITE_PRESCALING,
133 READOUT_RATES, READOUT_DAC, READOUT_ENABLE, READOUT_PRESCALING,
134 DO_PING_PONG);
135 signal FTU_control_State : FTU_control_StateType;
136
137begin
138
139 --FTU control finite state machine
140
141 FTU_control_FSM: process (clk_50MHz)
142
143 begin
144
145 reset_sig <= '0';
146
147 if Rising_edge(clk_50MHz) then
148
149 case FTU_control_State is
150
151 when IDLE => -- wait for DCMs to lock
152 if (clk_ready = '1') then
153 FTU_control_State <= INIT_DNA;
154 else
155 FTU_control_State <= IDLE;
156 end if;
157
158 when INIT_DNA => -- determine FPGA DNA
159 if (dna_ready = '1') then
160 FTU_control_State <= INIT_RAM;
161 dna_start <= '0';
162 else
163 dna_start <= '1';
164 FTU_control_State <= INIT_DNA;
165 end if;
166
167 when INIT_RAM => -- load default config data to RAM, see also ftu_definitions.vhd for more info
168 ram_ena_sig <= '1';
169 ram_wea_sig <= "1";
170 ram_ada_cntr <= ram_ada_cntr + 1;
171 ram_ada_sig <= conv_std_logic_vector(ram_ada_cntr, RAM_ADDR_WIDTH_A);
172 if (ram_ada_cntr < NO_OF_ENABLE*RAM_ADDR_RATIO) then -- default enables
173 if (ram_ada_cntr mod 2 = 0) then
174 ram_dia_sig <= DEFAULT_ENABLE(ram_ada_cntr / 2)(7 downto 0);
175 else
176 ram_dia_sig <= DEFAULT_ENABLE(ram_ada_cntr / 2)(15 downto 8);
177 end if;
178 FTU_control_State <= INIT_RAM;
179 elsif (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF)) then -- default counter values
180 ram_dia_sig <= (others => '0');
181 FTU_control_State <= INIT_RAM;
182 elsif (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO)) then -- default DACs
183 if (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)*RAM_ADDR_RATIO)) then
184 if (ram_ada_cntr mod 2 = 0) then
185 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF)) / 2),16)(7 downto 0);
186 else
187 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF)) / 2),16)(15 downto 8);
188 end if;
189 else
190 if (ram_ada_cntr mod 2 = 0) then
191 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC(((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF)) / 2) + NO_OF_DAC_NOT_USED),16)(7 downto 0);
192 else
193 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC(((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF)) / 2) + NO_OF_DAC_NOT_USED),16)(15 downto 8);
194 end if;
195 end if;
196 FTU_control_State <= INIT_RAM;
197 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO)) then -- default prescaling
198 ram_dia_sig <= conv_std_logic_vector(DEFAULT_PRESCALING,8);
199 FTU_control_State <= INIT_RAM;
200 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 1) then -- default overflow register
201 ram_dia_sig <= (others => '0');
202 FTU_control_State <= INIT_RAM;
203 elsif (ram_ada_cntr < 2**RAM_ADDR_WIDTH_A) then -- empty RAM cells
204 ram_dia_sig <= (others => '0');
205 FTU_control_State <= INIT_RAM;
206 else
207 ram_dia_sig <= (others => '0');
208 ram_ada_cntr <= 0;
209 ram_ada_sig <= (others => '0');
210 ram_ena_sig <= '0';
211 ram_wea_sig <= "0";
212 new_DACs_in_RAM <= '1';
213 new_enables_in_RAM <= '1';
214 new_prescaling_in_RAM <= '1';
215 cntr_reset_sig <= '1';
216 new_rates_busy <= '0';
217 FTU_control_State <= RUNNING;
218 end if;
219
220 when RUNNING => -- count triggers and react to commands from FTM
221 cntr_reset_sig <= '0';
222 config_start_sig <= '0';
223 if (new_rates_sig = '1') then -- counters have finished a period
224 FTU_control_State <= WRITE_RATES;
225 else -- update FTU settings if necessary
226 if (new_DACs_in_RAM = '1') then
227 ram_enb_sig <= '1';
228 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF), RAM_ADDR_WIDTH_B);
229 FTU_control_State <= CONFIG_DAC;
230 elsif (new_DACs_in_RAM = '0' and new_enables_in_RAM = '1') then
231 ram_enb_sig <= '1';
232 ram_adb_sig <= conv_std_logic_vector(0, RAM_ADDR_WIDTH_B);
233 FTU_control_State <= CONFIG_ENABLE;
234 elsif (new_DACs_in_RAM = '0' and new_enables_in_RAM = '0' and new_prescaling_in_RAM = '1') then
235 ram_ena_sig <= '1';
236 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A);
237 FTU_control_State <= CONFIG_COUNTER;
238 else -- nothing to be updated, check new commands from RS485
239 if (new_DACs = '1') then
240 FTU_control_State <= WRITE_DAC;
241 elsif (new_DACs = '0' and new_enables = '1') then
242 FTU_control_State <= WRITE_ENABLE;
243 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '1') then
244 FTU_control_State <= WRITE_PRESCALING;
245 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and
246 read_rates = '1') then
247 ram_enb_sig <= '1';
248 ram_adb_sig <= conv_std_logic_vector(NO_OF_ENABLE, RAM_ADDR_WIDTH_B);
249 FTU_control_State <= READOUT_RATES;
250 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and
251 read_rates = '0' and read_DACs = '1') then
252 ram_enb_sig <= '1';
253 ram_adb_sig <= conv_std_logic_vector(NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF, RAM_ADDR_WIDTH_B);
254 FTU_control_State <= READOUT_DAC;
255 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and
256 read_rates = '0' and read_DACs = '0' and read_enables = '1') then
257 ram_enb_sig <= '1';
258 ram_adb_sig <= conv_std_logic_vector(0, RAM_ADDR_WIDTH_B);
259 FTU_control_State <= READOUT_ENABLE;
260 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and
261 read_rates = '0' and read_DACs = '0' and read_enables = '0' and read_prescaling = '1') then
262 ram_ena_sig <= '1';
263 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A);
264 FTU_control_State <= READOUT_PRESCALING;
265 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and
266 read_rates = '0' and read_DACs = '0' and read_enables = '0' and read_prescaling = '0' and
267 ping_pong = '1') then
268 FTU_control_State <= DO_PING_PONG;
269 else
270 FTU_control_State <= RUNNING; --no commands from RS485 -> stay running
271 end if;
272 end if;
273 end if;
274
275 when CONFIG_COUNTER => -- set prescaling value for counters
276 wait_cntr <= wait_cntr + 1;
277 new_rates_busy <= '1';
278 if (wait_cntr = 0) then
279 FTU_control_State <= CONFIG_COUNTER;
280 elsif (wait_cntr = 1) then
281 prescaling_sig <= ram_doa;
282 FTU_control_State <= CONFIG_COUNTER;
283 prescaling_ready <= '1';
284 else
285 cntr_reset_sig <= '1';
286 ram_ada_sig <= (others => '0');
287 wait_cntr <= 0;
288 new_prescaling_in_RAM <= '0';
289 ram_ena_sig <= '0';
290 new_rates_busy <= '0';
291 prescaling_ready <= '0';
292 FTU_control_State <= RUNNING;
293 end if;
294
295 when CONFIG_ENABLE => -- set enable patterns for sum trigger stage
296 ram_enable_cntr <= ram_enable_cntr + 1;
297 new_rates_busy <= '1';
298 if (ram_enable_cntr = 0) then
299 ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
300 FTU_control_State <= CONFIG_ENABLE;
301 elsif (ram_enable_cntr < NO_OF_ENABLE) then
302 ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
303 enable_array_sig(ram_enable_cntr - 1) <= ram_dob;
304 FTU_control_State <= CONFIG_ENABLE;
305 elsif (ram_enable_cntr = NO_OF_ENABLE) then
306 ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
307 enable_array_sig(ram_enable_cntr - 1) <= ram_dob;
308 enables_ready <= '1';
309 FTU_control_State <= CONFIG_ENABLE;
310 else
311 ram_adb_sig <= (others => '0');
312 ram_enable_cntr <= 0;
313 new_enables_in_RAM <= '0';
314 ram_enb_sig <= '0';
315 cntr_reset_sig <= '1';
316 new_rates_busy <= '0';
317 enables_ready <= '0';
318 FTU_control_State <= RUNNING;
319 end if;
320
321 when CONFIG_DAC => -- start to set thresholds for sum trigger patches
322 new_rates_busy <= '1';
323 ram_dac_cntr <= ram_dac_cntr + 1;
324 if (ram_dac_cntr = 0) then
325 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);
326 FTU_control_State <= CONFIG_DAC;
327 elsif (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then
328 dac_array_sig(ram_dac_cntr - 1) <= conv_integer(unsigned(ram_dob(11 downto 0)));
329 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);
330 FTU_control_State <= CONFIG_DAC;
331 elsif (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED + 1)) then
332 dac_array_sig(4) <= 0;
333 dac_array_sig(5) <= 0;
334 dac_array_sig(6) <= 0;
335 dac_array_sig(ram_dac_cntr - 1 + NO_OF_DAC_NOT_USED) <= conv_integer(unsigned(ram_dob(11 downto 0)));
336 ram_adb_sig <= (others => '0');
337 FTU_control_State <= CONFIG_DAC;
338 DACs_ready <= '1';
339 else
340 ram_adb_sig <= (others => '0');
341 ram_enb_sig <= '0';
342 config_start_sig <= '1';
343 ram_dac_cntr <= 0;
344 DACs_ready <= '0';
345 FTU_control_State <= CONFIG_DAC_WAIT;
346 end if;
347
348 when CONFIG_DAC_WAIT => -- wait until setting of thresholds has finished
349 if (config_ready = '1') then
350 new_DACs_in_RAM <= '0';
351 cntr_reset_sig <= '1';
352 new_rates_busy <= '0';
353 config_start_sig <= '0';
354 FTU_control_State <= RUNNING;
355 elsif (config_ready = '0' and config_started = '1') then
356 new_rates_busy <= '1';
357 config_start_sig <= '0';
358 FTU_control_State <= CONFIG_DAC_WAIT;
359 else
360 new_rates_busy <= '1';
361 config_start_sig <= '1';
362 FTU_control_State <= CONFIG_DAC_WAIT;
363 end if;
364
365 when WRITE_RATES => -- write trigger/patch rates to RAM B and overflow register to RAM A
366 new_rates_busy <= '1';
367 ram_counter_cntr <= ram_counter_cntr + 1;
368 if (ram_counter_cntr < NO_OF_COUNTER*RAM_CEF) then
369 ram_enb_sig <= '1';
370 ram_web_sig <= "1";
371 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr), RAM_ADDR_WIDTH_B);
372 if (ram_counter_cntr mod 2 = 0) then
373 ram_dib_sig <= conv_std_logic_vector(rate_array_sig(ram_counter_cntr / 2), 32)(15 downto 0);
374 else
375 ram_dib_sig <= conv_std_logic_vector(rate_array_sig(ram_counter_cntr / 2), 32)(31 downto 16);
376 end if;
377 FTU_control_State <= WRITE_RATES;
378 elsif (ram_counter_cntr = NO_Of_COUNTER*RAM_CEF) then
379 ram_dib_sig <= (others => '0');
380 ram_adb_sig <= (others => '0');
381 ram_enb_sig <= '0';
382 ram_web_sig <= "0";
383 ram_ena_sig <= '1';
384 ram_wea_sig <= "1";
385 ram_ada_sig <= conv_std_logic_vector(NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1, RAM_ADDR_WIDTH_A);
386 ram_dia_sig <= overflow_array;
387 FTU_control_State <= WRITE_RATES;
388 else
389 ram_ena_sig <= '0';
390 ram_wea_sig <= "0";
391 ram_counter_cntr <= 0;
392 new_rates_busy <= '0';
393 FTU_control_State <= RUNNING;
394 end if;
395
396 when WRITE_DAC => -- write new DAC values from RS485 to RAM
397 ram_dac_cntr <= ram_dac_cntr + 1;
398 if (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)) then
399 ram_enb_sig <= '1';
400 ram_web_sig <= "1";
401 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + ram_dac_cntr), RAM_ADDR_WIDTH_B);
402 ram_dib_sig <= conv_std_logic_vector(dac_array_rs485_out(ram_dac_cntr), 16);
403 FTU_control_State <= WRITE_DAC;
404 elsif (ram_dac_cntr = (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)) then
405 ram_enb_sig <= '1';
406 ram_web_sig <= "1";
407 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + ram_dac_cntr), RAM_ADDR_WIDTH_B);
408 ram_dib_sig <= conv_std_logic_vector(dac_array_rs485_out(ram_dac_cntr + NO_OF_DAC_NOT_USED), 16);
409 FTU_control_State <= WRITE_DAC;
410 else
411 ram_enb_sig <= '0';
412 ram_web_sig <= "0";
413 new_DACs_in_RAM <= '1';
414 ram_dib_sig <= (others => '0');
415 ram_adb_sig <= (others => '0');
416 ram_dac_cntr <= 0;
417 FTU_control_State <= RUNNING;
418 end if;
419
420 when WRITE_ENABLE => -- write new enable patterns from RS485 to RAM
421 ram_enable_cntr <= ram_enable_cntr + 1;
422 if (ram_enable_cntr < NO_OF_ENABLE) then
423 ram_enb_sig <= '1';
424 ram_web_sig <= "1";
425 ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr, RAM_ADDR_WIDTH_B);
426 ram_dib_sig <= enable_array_rs485_out(ram_enable_cntr);
427 else
428 ram_enb_sig <= '0';
429 ram_web_sig <= "0";
430 new_enables_in_RAM <= '1';
431 ram_dib_sig <= (others => '0');
432 ram_adb_sig <= (others => '0');
433 ram_enable_cntr <= 0;
434 FTU_control_State <= RUNNING;
435 end if;
436
437 when WRITE_PRESCALING => -- write new prescaling from RS485 to RAM
438 wait_cntr <= wait_cntr + 1;
439 if (wait_cntr = 0) then
440 ram_ena_sig <= '1';
441 ram_wea_sig <= "1";
442 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A);
443 ram_dia_sig <= prescaling_rs485_out;
444 else
445 ram_ena_sig <= '0';
446 ram_wea_sig <= "0";
447 new_prescaling_in_RAM <= '1';
448 ram_dia_sig <= (others => '0');
449 ram_ada_sig <= (others => '0');
450 wait_cntr <= 0;
451 FTU_control_State <= RUNNING;
452 end if;
453
454 when READOUT_RATES => -- read most recent rate values from RAM and send them to RS485 module
455 ram_counter_cntr <= ram_counter_cntr + 1;
456 if (ram_counter_cntr = 0) then
457 ram_enb_sig <= '1';
458 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr + 1), RAM_ADDR_WIDTH_B);
459 FTU_control_State <= READOUT_RATES;
460 elsif (ram_counter_cntr < 3) then
461 ram_ena_sig <= '1';
462 ram_ada_sig <= conv_std_logic_vector(((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1), RAM_ADDR_WIDTH_A);
463 ram_enb_sig <= '1';
464 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr + 1), RAM_ADDR_WIDTH_B);
465 if (ram_counter_cntr = 1) then
466 ram_buffer_sig(15 downto 0) <= ram_dob;
467 else
468 ram_buffer_sig(29 downto 16) <= ram_dob(13 downto 0);
469 end if;
470 FTU_control_State <= READOUT_RATES;
471 elsif (ram_counter_cntr < NO_OF_COUNTER*RAM_CEF) then
472 ram_ena_sig <= '1';
473 ram_ada_sig <= conv_std_logic_vector(((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1), RAM_ADDR_WIDTH_A);
474 ram_enb_sig <= '1';
475 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr + 1), RAM_ADDR_WIDTH_B);
476 if (ram_counter_cntr mod 2 = 1) then
477 ram_buffer_sig(15 downto 0) <= ram_dob;
478 rate_array_rs485((ram_counter_cntr / 2) - 1) <= conv_integer(unsigned(ram_buffer_sig));
479 else
480 ram_buffer_sig(29 downto 16) <= ram_dob(13 downto 0);
481 end if;
482 FTU_control_State <= READOUT_RATES;
483 elsif (ram_counter_cntr = NO_Of_COUNTER*RAM_CEF) then
484 ram_enb_sig <= '0';
485 ram_adb_sig <= (others => '0');
486 ram_buffer_sig(29 downto 16) <= ram_dob(13 downto 0);
487 ram_ena_sig <= '1';
488 ram_ada_sig <= conv_std_logic_vector(((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1), RAM_ADDR_WIDTH_A);
489 FTU_control_State <= READOUT_RATES;
490 elsif (ram_counter_cntr = NO_Of_COUNTER*RAM_CEF + 1) then
491 rate_array_rs485((ram_counter_cntr / 2) - 1) <= conv_integer(unsigned(ram_buffer_sig));
492 ram_buffer_sig <= (others => '0');
493 ram_enb_sig <= '0';
494 ram_adb_sig <= (others => '0');
495 ram_ena_sig <= '0';
496 ram_ada_sig <= (others => '0');
497 overflow_array_rs485_in <= ram_doa;
498 rates_ready <= '1';
499 FTU_control_State <= READOUT_RATES;
500 else
501 ram_enb_sig <= '0';
502 ram_adb_sig <= (others => '0');
503 ram_ena_sig <= '0';
504 ram_ada_sig <= (others => '0');
505 ram_counter_cntr <= 0;
506 rates_ready <= '0';
507 FTU_control_State <= RUNNING;
508 end if;
509
510 when READOUT_DAC => -- read most recent DAC values from RAM and send them to RS485 module
511 ram_dac_cntr <= ram_dac_cntr + 1;
512 if (ram_dac_cntr = 0) then
513 ram_enb_sig <= '1';
514 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);
515 FTU_control_State <= READOUT_DAC;
516 elsif (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then
517 ram_enb_sig <= '1';
518 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER*RAM_CEF + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);
519 dac_array_sig(ram_dac_cntr - 1) <= conv_integer(unsigned(ram_dob(11 downto 0)));
520 FTU_control_State <= READOUT_DAC;
521 elsif (ram_dac_cntr = (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then
522 ram_enb_sig <= '0';
523 ram_adb_sig <= (others => '0');
524 dac_array_sig(ram_dac_cntr + NO_OF_DAC_NOT_USED - 1) <= conv_integer(unsigned(ram_dob(11 downto 0)));
525 DACs_ready <= '1';
526 FTU_control_State <= READOUT_DAC;
527 else
528 ram_enb_sig <= '0';
529 ram_adb_sig <= (others => '0');
530 DACs_ready <= '0';
531 ram_dac_cntr <= 0;
532 FTU_control_State <= RUNNING;
533 end if;
534
535 when READOUT_ENABLE => -- read most recent enable patterns from RAM and send them to RS485 module
536 ram_enable_cntr <= ram_enable_cntr + 1;
537 if (ram_enable_cntr = 0) then
538 ram_enb_sig <= '1';
539 ram_adb_sig <= conv_std_logic_vector((ram_enable_cntr + 1), RAM_ADDR_WIDTH_B);
540 FTU_control_State <= READOUT_ENABLE;
541 elsif (ram_enable_cntr < NO_OF_ENABLE) then
542 ram_enb_sig <= '1';
543 ram_adb_sig <= conv_std_logic_vector((ram_enable_cntr + 1), RAM_ADDR_WIDTH_B);
544 enable_array_sig(ram_enable_cntr - 1) <= ram_dob;
545 FTU_control_State <= READOUT_ENABLE;
546 elsif (ram_enable_cntr = NO_OF_ENABLE) then
547 ram_enb_sig <= '0';
548 ram_adb_sig <= (others => '0');
549 enable_array_sig(ram_enable_cntr - 1) <= ram_dob;
550 enables_ready <= '1';
551 FTU_control_State <= READOUT_ENABLE;
552 else
553 ram_enb_sig <= '0';
554 ram_adb_sig <= (others => '0');
555 enables_ready <= '0';
556 ram_enable_cntr <= 0;
557 FTU_control_State <= RUNNING;
558 end if;
559
560 when READOUT_PRESCALING => -- read most recent prescaling value from RAM and send it to RS485 module
561 wait_cntr <= wait_cntr + 1;
562 if (wait_cntr = 0) then
563 ram_ena_sig <= '1';
564 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO*RAM_CEF + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 1, RAM_ADDR_WIDTH_A);
565 FTU_control_State <= READOUT_PRESCALING;
566 elsif (wait_cntr = 1) then
567 ram_ena_sig <= '1';
568 ram_ada_sig <= (others => '0');
569 prescaling_sig <= ram_doa;
570 FTU_control_State <= READOUT_PRESCALING;
571 elsif (wait_cntr = 2) then
572 ram_ena_sig <= '0';
573 ram_ada_sig <= (others => '0');
574 overflow_array_rs485_in <= ram_doa;
575 prescaling_ready <= '1';
576 FTU_control_State <= READOUT_PRESCALING;
577 else
578 ram_ena_sig <= '0';
579 ram_ada_sig <= (others => '0');
580 prescaling_ready <= '0';
581 wait_cntr <= 0;
582 FTU_control_State <= RUNNING;
583 end if;
584
585 when DO_PING_PONG => -- answer to FTM and send DNA
586 wait_cntr <= wait_cntr + 1;
587 if (wait_cntr = 0) then
588 ping_pong_ready <= '1';
589 FTU_control_State <= DO_PING_PONG;
590 else
591 ping_pong_ready <= '0';
592 wait_cntr <= 0;
593 FTU_control_State <= RUNNING;
594 end if;
595
596 end case;
597 end if;
598 end process FTU_control_FSM;
599
600 detect_new_rates: process(clk_50MHz)
601 begin
602 if rising_edge(clk_50MHz) then
603 new_rates_sr <= new_rates_sr(new_rates_sr'left - 1 downto 0) & new_rates;
604 if(new_rates_busy = '1') then
605 new_rates_sig <= '0';
606 else
607 if (new_rates_sr(1 downto 0) = "01") then
608 new_rates_sig <= '1';
609 end if;
610 end if;
611 end if;
612 end process detect_new_rates;
613
614 reset <= reset_sig;
615
616 config_start <= config_start_sig;
617 dac_array <= dac_array_sig;
618
619 enable_array <= enable_array_sig;
620 prescaling <= prescaling_sig;
621
622 rate_array_sig <= rate_array;
623 cntr_reset <= cntr_reset_sig;
624
625 ram_ena <= ram_ena_sig;
626 ram_enb <= ram_enb_sig;
627 ram_wea <= ram_wea_sig;
628 ram_web <= ram_web_sig;
629 ram_ada <= ram_ada_sig;
630 ram_adb <= ram_adb_sig;
631 ram_dia <= ram_dia_sig;
632 ram_dib <= ram_dib_sig;
633
634end Behavioral;
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