source: firmware/FTU/FTU_control.vhd@ 9880

Last change on this file since 9880 was 9880, checked in by weitzel, 15 years ago
FTU_rate_counter added and FTU_control state machine extended
File size: 12.8 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 08/06/2010
6-- Design Name:
7-- Module Name: FTU_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Control FSM of FACT FTU board
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20
21library IEEE;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.STD_LOGIC_ARITH.ALL;
24use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
26library ftu_definitions;
27USE ftu_definitions.ftu_array_types.all;
28USE ftu_definitions.ftu_constants.all;
29
30---- Uncomment the following library declaration if instantiating
31---- any Xilinx primitives in this code.
32--library UNISIM;
33--use UNISIM.VComponents.all;
34
35entity FTU_control is
36 port(
37 clk_50MHz : IN std_logic;
38 clk_ready : IN std_logic;
39 config_started : IN std_logic;
40 config_ready : IN std_logic;
41 ram_doa : IN STD_LOGIC_VECTOR(7 downto 0);
42 ram_dob : IN STD_LOGIC_VECTOR(15 downto 0);
43 rate_array : IN rate_array_type;
44 reset : OUT std_logic;
45 config_start : OUT std_logic;
46 ram_ena : OUT std_logic;
47 ram_enb : OUT std_logic;
48 ram_wea : OUT STD_LOGIC_VECTOR(0 downto 0);
49 ram_web : OUT STD_LOGIC_VECTOR(0 downto 0);
50 ram_ada : OUT STD_LOGIC_VECTOR(4 downto 0);
51 ram_adb : OUT STD_LOGIC_VECTOR(3 downto 0);
52 ram_dia : OUT STD_LOGIC_VECTOR(7 downto 0);
53 ram_dib : OUT STD_LOGIC_VECTOR(15 downto 0);
54 dac_array : OUT dac_array_type;
55 enable_array : OUT enable_array_type;
56 cntr_reset : OUT STD_LOGIC;
57 prescaling : OUT STD_LOGIC_VECTOR(7 downto 0)
58 );
59end FTU_control;
60
61architecture Behavioral of FTU_control is
62
63 signal reset_sig : STD_LOGIC := '0'; --initialize reset to 0 at power up
64
65 --DAC/SPI interface, default DACs come from RAM during INIT
66 signal config_start_sig : STD_LOGIC := '0';
67 signal dac_array_sig : dac_array_type := (0,0,0,0,0,0,0,0);
68
69 --enable signals for pixels in trigger, default values come from RAM during INIT
70 signal enable_array_sig : enable_array_type := ("0000000000000000", --patch A
71 "0000000000000000", --patch B
72 "0000000000000000", --patch C
73 "0000000000000000");--patch D
74
75 signal rate_array_sig : rate_array_type; -- initialized in FTU_top
76 signal cntr_reset_sig : STD_LOGIC := '0';
77 signal prescaling_sig : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
78
79 signal ram_ena_sig : STD_LOGIC := '0'; -- RAM enable for port A
80 signal ram_enb_sig : STD_LOGIC := '0'; -- RAM enable for port B
81 signal ram_wea_sig : STD_LOGIC_VECTOR(0 downto 0) := "0"; -- RAM write enable for port A
82 signal ram_web_sig : STD_LOGIC_VECTOR(0 downto 0) := "0"; -- RAM write enable for port B
83 signal ram_ada_sig : STD_LOGIC_VECTOR(4 downto 0) := (others => '0'); --RAM port A address
84 signal ram_adb_sig : STD_LOGIC_VECTOR(3 downto 0) := (others => '0'); --RAM port B address
85 signal ram_dia_sig : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); --RAM data in A
86 signal ram_dib_sig : STD_LOGIC_VECTOR(15 downto 0) := (others => '0'); --RAM data in B
87
88 --counter to loop through RAM
89 signal ram_ada_cntr : INTEGER range 0 to 2**RAM_ADDR_WIDTH_A := 0;
90 signal ram_adb_cntr : INTEGER range 0 to 2**RAM_ADDR_WIDTH_B := 0;
91 signal ram_dac_cntr : INTEGER range 0 to (NO_OF_DAC - NO_OF_DAC_NOT_USED + 2) := 0;
92 signal ram_enable_cntr : INTEGER range 0 to (NO_OF_ENABLE + 1) := 0;
93
94 signal wait_cntr : INTEGER range 0 to 2**RAM_ADDR_WIDTH_A := 0;
95
96 signal new_DACs_in_RAM : STD_LOGIC := '0';
97 signal new_enables_in_RAM : STD_LOGIC := '0';
98 signal new_prescaling_in_RAM : STD_LOGIC := '0';
99
100 type FTU_control_StateType is (IDLE, INIT, RUNNING, CONFIG_ENABLE, CONFIG_DAC, CONFIG_COUNTER, RESET_ALL);
101 signal FTU_control_State : FTU_control_StateType;
102
103begin
104
105 --FTU control finite state machine
106
107 FTU_control_FSM: process (clk_50MHz)
108
109 begin
110
111 if Rising_edge(clk_50MHz) then
112
113 case FTU_control_State is
114
115 when IDLE => -- wait for DCMs to lock
116 reset_sig <= '0';
117 config_start_sig <= '0';
118 ram_ena_sig <= '0';
119 ram_wea_sig <= "0";
120 if (clk_ready = '1') then
121 FTU_control_State <= INIT;
122 end if;
123
124 when INIT => -- load default config data to RAM, see also ftu_definitions.vhd for more info
125 reset_sig <= '0';
126 config_start_sig <= '0';
127 ram_ena_sig <= '1';
128 ram_wea_sig <= "1";
129 ram_ada_cntr <= ram_ada_cntr + 1;
130 ram_ada_sig <= conv_std_logic_vector(ram_ada_cntr, RAM_ADDR_WIDTH_A);
131 if (ram_ada_cntr < NO_OF_ENABLE*RAM_ADDR_RATIO) then -- default enables
132 if (ram_ada_cntr mod 2 = 0) then
133 ram_dia_sig <= DEFAULT_ENABLE(ram_ada_cntr / 2)(7 downto 0);
134 else
135 ram_dia_sig <= DEFAULT_ENABLE(ram_ada_cntr / 2)(15 downto 8);
136 end if;
137 FTU_control_State <= INIT;
138 elsif (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) then -- default counter values
139 ram_dia_sig <= (others => '0');
140 FTU_control_State <= INIT;
141 elsif (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO)) then -- default DACs
142 if (ram_ada_cntr < NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)*RAM_ADDR_RATIO) then
143 if (ram_ada_cntr mod 2 = 0) then
144 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) / 2),16)(7 downto 0);
145 else
146 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) / 2),16)(15 downto 8);
147 end if;
148 else
149 if (ram_ada_cntr mod 2 = 0) then
150 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC(((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) / 2) + NO_OF_DAC_NOT_USED),16)(7 downto 0);
151 else
152 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC(((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) / 2) + NO_OF_DAC_NOT_USED),16)(15 downto 8);
153 end if;
154 end if;
155 FTU_control_State <= INIT;
156 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO)) then -- default prescaling
157 ram_dia_sig <= conv_std_logic_vector(DEFAULT_PRESCALING,8);
158 FTU_control_State <= INIT;
159 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 1) then -- default overflow register
160 ram_dia_sig <= (others => '0');
161 FTU_control_State <= INIT;
162 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 2) then -- default checksum
163 ram_dia_sig <= (others => '0');
164 FTU_control_State <= INIT;
165 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 3) then -- empty RAM cell
166 ram_dia_sig <= (others => '0');
167 FTU_control_State <= INIT;
168 else
169 ram_dia_sig <= (others => '0');
170 ram_ada_cntr <= 0;
171 ram_ada_sig <= (others => '0');
172 ram_ena_sig <= '0';
173 ram_wea_sig <= "0";
174 new_DACs_in_RAM <= '1';
175 new_enables_in_RAM <= '1';
176 new_prescaling_in_RAM <= '1';
177 FTU_control_State <= RUNNING;
178 end if;
179
180 when RUNNING => -- count triggers and react to commands from FTM
181 reset_sig <= '0';
182 config_start_sig <= '0';
183 if (new_DACs_in_RAM = '1') then
184 ram_enb_sig <= '1';
185 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER), RAM_ADDR_WIDTH_B);
186 FTU_control_State <= CONFIG_DAC;
187 elsif (new_DACs_in_RAM = '0' and new_enables_in_RAM = '1') then
188 ram_enb_sig <= '1';
189 ram_adb_sig <= conv_std_logic_vector(0, RAM_ADDR_WIDTH_B);
190 FTU_control_State <= CONFIG_ENABLE;
191 elsif (new_DACs_in_RAM = '0' and new_enables_in_RAM = '0' and new_prescaling_in_RAM = '1') then
192 ram_ena_sig <= '1';
193 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A);
194 FTU_control_State <= CONFIG_COUNTER;
195 else
196 FTU_control_State <= RUNNING;
197 end if;
198
199 when CONFIG_COUNTER =>
200 wait_cntr <= wait_cntr + 1;
201 if (wait_cntr = 0) then
202 FTU_control_State <= CONFIG_COUNTER;
203 elsif (wait_cntr = 1) then
204 prescaling_sig <= ram_doa;
205 cntr_reset_sig <= '1';
206 FTU_control_State <= CONFIG_COUNTER;
207 else
208 cntr_reset_sig <= '0';
209 ram_ada_sig <= (others => '0');
210 wait_cntr <= 0;
211 new_prescaling_in_RAM <= '0';
212 ram_ena_sig <= '0';
213 FTU_control_State <= RUNNING;
214 end if;
215
216 when CONFIG_ENABLE =>
217 ram_enable_cntr <= ram_enable_cntr + 1;
218 if (ram_enable_cntr = 0) then
219 ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
220 FTU_control_State <= CONFIG_ENABLE;
221 elsif (ram_enable_cntr > 0 and ram_enable_cntr < NO_OF_ENABLE + 1) then
222 ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
223 enable_array_sig(ram_enable_cntr - 1) <= ram_dob;
224 FTU_control_State <= CONFIG_ENABLE;
225 else
226 ram_adb_sig <= (others => '0');
227 ram_enable_cntr <= 0;
228 new_enables_in_RAM <= '0';
229 ram_enb_sig <= '0';
230 FTU_control_State <= RUNNING;
231 end if;
232
233 when CONFIG_DAC =>
234 if (ram_dac_cntr <= (NO_OF_DAC - NO_OF_DAC_NOT_USED + 2)) then
235 ram_dac_cntr <= ram_dac_cntr + 1;
236 if (ram_dac_cntr = 0) then
237 FTU_control_State <= CONFIG_DAC;
238 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);
239 elsif (ram_dac_cntr > 0 and ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then
240 dac_array_sig(ram_dac_cntr - 1) <= conv_integer(unsigned(ram_dob));
241 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);
242 FTU_control_State <= CONFIG_DAC;
243 elsif (ram_dac_cntr > 0 and ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED + 1)) then
244 dac_array_sig(ram_dac_cntr - 1 + NO_OF_DAC_NOT_USED) <= conv_integer(unsigned(ram_dob));
245 ram_adb_sig <= (others => '0');
246 FTU_control_State <= CONFIG_DAC;
247 else
248 ram_adb_sig <= (others => '0');
249 config_start_sig <= '1';
250 FTU_control_State <= CONFIG_DAC;
251 end if;
252 else
253 if (config_ready = '1') then
254 ram_dac_cntr <= 0;
255 new_DACs_in_RAM <= '0';
256 FTU_control_State <= RUNNING;
257 elsif (config_ready = '0' and config_started = '1') then
258 ram_enb_sig <= '0';
259 config_start_sig <= '0';
260 FTU_control_State <= CONFIG_DAC;
261 else
262 FTU_control_State <= CONFIG_DAC;
263 end if;
264 end if;
265
266 when RESET_ALL => -- reset/clear and start from scratch
267 reset_sig <= '1';
268 config_start_sig <= '0';
269 FTU_control_State <= IDLE;
270 end case;
271 end if;
272 end process FTU_control_FSM;
273
274 reset <= reset_sig;
275
276 config_start <= config_start_sig;
277 dac_array <= dac_array_sig;
278
279 enable_array <= enable_array_sig;
280
281 rate_array_sig <= rate_array;
282 cntr_reset <= cntr_reset_sig;
283 prescaling <= prescaling_sig;
284
285 ram_ena <= ram_ena_sig;
286 ram_enb <= ram_enb_sig;
287 ram_wea <= ram_wea_sig;
288 ram_web <= ram_web_sig;
289 ram_ada <= ram_ada_sig;
290 ram_adb <= ram_adb_sig;
291 ram_dia <= ram_dia_sig;
292 ram_dib <= ram_dib_sig;
293
294end Behavioral;
Note: See TracBrowser for help on using the repository browser.