source: firmware/FTU/FTU_control.vhd@ 9968

Last change on this file since 9968 was 9939, checked in by weitzel, 15 years ago
FTU RS485 interface is now connected to main control
File size: 26.9 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 08/06/2010
6-- Design Name:
7-- Module Name: FTU_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Control FSM of FACT FTU board
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20
21library IEEE;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.STD_LOGIC_ARITH.ALL;
24use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
26library ftu_definitions;
27USE ftu_definitions.ftu_array_types.all;
28USE ftu_definitions.ftu_constants.all;
29
30---- Uncomment the following library declaration if instantiating
31---- any Xilinx primitives in this code.
32--library UNISIM;
33--use UNISIM.VComponents.all;
34
35entity FTU_control is
36 port(
37 clk_50MHz : IN std_logic;
38 clk_ready : IN std_logic; -- from DCM
39 config_started : IN std_logic; -- from DAC/SPI
40 config_ready : IN std_logic; -- from DAC/SPI
41 ram_doa : IN STD_LOGIC_VECTOR(7 downto 0);
42 ram_dob : IN STD_LOGIC_VECTOR(15 downto 0);
43 rate_array : IN rate_array_type; -- from counters
44 overflow_array : IN STD_LOGIC_VECTOR(7 downto 0); -- from counters
45 new_rates : IN std_logic; -- from counters
46 new_DACs : IN std_logic; -- from RS485 module
47 new_enables : IN std_logic; -- from RS485 module
48 new_prescaling : IN std_logic; -- from RS485 module
49 read_rates : IN std_logic; -- from RS485 module
50 read_DACs : IN std_logic; -- from RS485 module
51 read_enables : IN std_logic; -- from RS485 module
52 read_prescaling : IN std_logic; -- from RS485 module
53 dac_array_rs485_out : IN dac_array_type; -- from RS485 module
54 enable_array_rs485_out : IN enable_array_type; -- from RS485 module
55 prescaling_rs485_out : IN STD_LOGIC_VECTOR(7 downto 0); -- from RS485 module
56 reset : OUT std_logic;
57 config_start : OUT std_logic;
58 ram_ena : OUT std_logic;
59 ram_enb : OUT std_logic;
60 ram_wea : OUT STD_LOGIC_VECTOR(0 downto 0);
61 ram_web : OUT STD_LOGIC_VECTOR(0 downto 0);
62 ram_ada : OUT STD_LOGIC_VECTOR(4 downto 0);
63 ram_adb : OUT STD_LOGIC_VECTOR(3 downto 0);
64 ram_dia : OUT STD_LOGIC_VECTOR(7 downto 0);
65 ram_dib : OUT STD_LOGIC_VECTOR(15 downto 0);
66 rate_array_rs485 : OUT rate_array_type := (0,0,0,0,0); -- to RS485 module
67 overflow_array_rs485_in : OUT STD_LOGIC_VECTOR(7 downto 0) := "00000000"; -- to RS485 module
68 rates_ready : OUT std_logic := '0'; -- to RS485 module
69 DACs_ready : OUT std_logic := '0'; -- to RS485 module
70 enables_ready : OUT std_logic := '0'; -- to RS485 module
71 prescaling_ready : OUT std_logic := '0'; -- to RS485 module
72 dac_array : OUT dac_array_type;
73 enable_array : OUT enable_array_type;
74 cntr_reset : OUT STD_LOGIC;
75 prescaling : OUT STD_LOGIC_VECTOR(7 downto 0)
76 );
77end FTU_control;
78
79architecture Behavioral of FTU_control is
80
81 signal reset_sig : STD_LOGIC := '0'; --initialize reset to 0 at power up
82
83 --DAC/SPI interface, default DACs come from RAM during INIT
84 signal config_start_sig : STD_LOGIC := '0';
85 signal dac_array_sig : dac_array_type := (0,0,0,0,0,0,0,0);
86
87 --enable signals for pixels in trigger, default values come from RAM during INIT
88 signal enable_array_sig : enable_array_type := ("0000000000000000", --patch A
89 "0000000000000000", --patch B
90 "0000000000000000", --patch C
91 "0000000000000000");--patch D
92
93 signal rate_array_sig : rate_array_type; -- initialized in FTU_top
94 signal cntr_reset_sig : STD_LOGIC := '0';
95 signal prescaling_sig : STD_LOGIC_VECTOR(7 downto 0) := "00011101"; -- 29
96
97 signal ram_ena_sig : STD_LOGIC := '0'; -- RAM enable for port A
98 signal ram_enb_sig : STD_LOGIC := '0'; -- RAM enable for port B
99 signal ram_wea_sig : STD_LOGIC_VECTOR(0 downto 0) := "0"; -- RAM write enable for port A
100 signal ram_web_sig : STD_LOGIC_VECTOR(0 downto 0) := "0"; -- RAM write enable for port B
101 signal ram_ada_sig : STD_LOGIC_VECTOR(4 downto 0) := (others => '0'); --RAM port A address
102 signal ram_adb_sig : STD_LOGIC_VECTOR(3 downto 0) := (others => '0'); --RAM port B address
103 signal ram_dia_sig : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); --RAM data in A
104 signal ram_dib_sig : STD_LOGIC_VECTOR(15 downto 0) := (others => '0'); --RAM data in B
105
106 --counter to loop through RAM
107 signal ram_ada_cntr : INTEGER range 0 to 2**RAM_ADDR_WIDTH_A := 0;
108 signal ram_dac_cntr : INTEGER range 0 to (NO_OF_DAC - NO_OF_DAC_NOT_USED + 2) := 0;
109 signal ram_enable_cntr : INTEGER range 0 to (NO_OF_ENABLE + 1) := 0;
110 signal ram_counter_cntr : INTEGER range 0 to (NO_OF_COUNTER + 2) := 0; --includes overflow register
111
112 signal wait_cntr : INTEGER range 0 to 2**RAM_ADDR_WIDTH_A := 0;
113
114 signal new_rates_sig : STD_LOGIC := '0';
115 signal new_rates_busy : STD_LOGIC := '0';
116
117 signal new_DACs_in_RAM : STD_LOGIC := '0';
118 signal new_enables_in_RAM : STD_LOGIC := '0';
119 signal new_prescaling_in_RAM : STD_LOGIC := '0';
120
121 type FTU_control_StateType is (IDLE, INIT, RUNNING,
122 CONFIG_ENABLE, CONFIG_DAC, CONFIG_COUNTER,
123 WRITE_RATES, WRITE_DAC, WRITE_ENABLE, WRITE_PRESCALING,
124 READOUT_RATES, READOUT_DAC, READOUT_ENABLE, READOUT_PRESCALING);
125 signal FTU_control_State : FTU_control_StateType;
126
127begin
128
129 --FTU control finite state machine
130
131 FTU_control_FSM: process (clk_50MHz)
132
133 begin
134
135 reset_sig <= '0';
136
137 if Rising_edge(clk_50MHz) then
138
139 case FTU_control_State is
140
141 when IDLE => -- wait for DCMs to lock
142 config_start_sig <= '0';
143 ram_ena_sig <= '0';
144 ram_wea_sig <= "0";
145 if (clk_ready = '1') then
146 FTU_control_State <= INIT;
147 else
148 FTU_control_State <= IDLE;
149 end if;
150
151 when INIT => -- load default config data to RAM, see also ftu_definitions.vhd for more info
152 new_rates_busy <= '1';
153 config_start_sig <= '0';
154 ram_ena_sig <= '1';
155 ram_wea_sig <= "1";
156 ram_ada_cntr <= ram_ada_cntr + 1;
157 ram_ada_sig <= conv_std_logic_vector(ram_ada_cntr, RAM_ADDR_WIDTH_A);
158 if (ram_ada_cntr < NO_OF_ENABLE*RAM_ADDR_RATIO) then -- default enables
159 if (ram_ada_cntr mod 2 = 0) then
160 ram_dia_sig <= DEFAULT_ENABLE(ram_ada_cntr / 2)(7 downto 0);
161 else
162 ram_dia_sig <= DEFAULT_ENABLE(ram_ada_cntr / 2)(15 downto 8);
163 end if;
164 FTU_control_State <= INIT;
165 elsif (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) then -- default counter values
166 ram_dia_sig <= (others => '0');
167 FTU_control_State <= INIT;
168 elsif (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO)) then -- default DACs
169 if (ram_ada_cntr < (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)*RAM_ADDR_RATIO)) then
170 if (ram_ada_cntr mod 2 = 0) then
171 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) / 2),16)(7 downto 0);
172 else
173 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) / 2),16)(15 downto 8);
174 end if;
175 else
176 if (ram_ada_cntr mod 2 = 0) then
177 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC(((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) / 2) + NO_OF_DAC_NOT_USED),16)(7 downto 0);
178 else
179 ram_dia_sig <= conv_std_logic_vector(DEFAULT_DAC(((ram_ada_cntr - (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO)) / 2) + NO_OF_DAC_NOT_USED),16)(15 downto 8);
180 end if;
181 end if;
182 FTU_control_State <= INIT;
183 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO)) then -- default prescaling
184 ram_dia_sig <= conv_std_logic_vector(DEFAULT_PRESCALING,8);
185 FTU_control_State <= INIT;
186 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 1) then -- default overflow register
187 ram_dia_sig <= (others => '0');
188 FTU_control_State <= INIT;
189 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 2) then -- default checksum
190 ram_dia_sig <= (others => '0');
191 FTU_control_State <= INIT;
192 elsif (ram_ada_cntr = (NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 3) then -- empty RAM cell
193 ram_dia_sig <= (others => '0');
194 FTU_control_State <= INIT;
195 else
196 ram_dia_sig <= (others => '0');
197 ram_ada_cntr <= 0;
198 ram_ada_sig <= (others => '0');
199 ram_ena_sig <= '0';
200 ram_wea_sig <= "0";
201 new_DACs_in_RAM <= '1';
202 new_enables_in_RAM <= '1';
203 new_prescaling_in_RAM <= '1';
204 cntr_reset_sig <= '1';
205 new_rates_busy <= '0';
206 FTU_control_State <= RUNNING;
207 end if;
208
209 when RUNNING => -- count triggers and react to commands from FTM
210 cntr_reset_sig <= '0';
211 config_start_sig <= '0';
212 if (new_rates_sig = '1') then -- counters have finished a period
213 FTU_control_State <= WRITE_RATES;
214 else -- update FTU settings if necessary
215 if (new_DACs_in_RAM = '1') then
216 ram_enb_sig <= '1';
217 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER), RAM_ADDR_WIDTH_B);
218 FTU_control_State <= CONFIG_DAC;
219 elsif (new_DACs_in_RAM = '0' and new_enables_in_RAM = '1') then
220 ram_enb_sig <= '1';
221 ram_adb_sig <= conv_std_logic_vector(0, RAM_ADDR_WIDTH_B);
222 FTU_control_State <= CONFIG_ENABLE;
223 elsif (new_DACs_in_RAM = '0' and new_enables_in_RAM = '0' and new_prescaling_in_RAM = '1') then
224 ram_ena_sig <= '1';
225 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A);
226 FTU_control_State <= CONFIG_COUNTER;
227 else -- nothing to be updated, check new commands from RS485
228 if (new_DACs = '1') then
229 FTU_control_State <= WRITE_DAC;
230 elsif (new_DACs = '0' and new_enables = '1') then
231 FTU_control_State <= WRITE_ENABLE;
232 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '1') then
233 FTU_control_State <= WRITE_PRESCALING;
234 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and
235 read_rates = '1') then
236 ram_enb_sig <= '1';
237 ram_adb_sig <= conv_std_logic_vector(NO_OF_ENABLE, RAM_ADDR_WIDTH_B);
238 FTU_control_State <= READOUT_RATES;
239 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and
240 read_rates = '0' and read_DACs = '1') then
241 ram_enb_sig <= '1';
242 ram_adb_sig <= conv_std_logic_vector(NO_OF_ENABLE + NO_OF_COUNTER, RAM_ADDR_WIDTH_B);
243 FTU_control_State <= READOUT_DAC;
244 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and
245 read_rates = '0' and read_DACs = '0' and read_enables = '1') then
246 ram_enb_sig <= '1';
247 ram_adb_sig <= conv_std_logic_vector(0, RAM_ADDR_WIDTH_B);
248 FTU_control_State <= READOUT_ENABLE;
249 elsif (new_DACs = '0' and new_enables = '0' and new_prescaling = '0' and
250 read_rates = '0' and read_DACs = '0' and read_enables = '0' and read_prescaling = '1') then
251 ram_ena_sig <= '1';
252 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A);
253 FTU_control_State <= READOUT_PRESCALING;
254 else
255 FTU_control_State <= RUNNING; --no commands from RS485 -> stay running
256 end if;
257 end if;
258 end if;
259
260 when CONFIG_COUNTER =>
261 wait_cntr <= wait_cntr + 1;
262 new_rates_busy <= '1';
263 if (wait_cntr = 0) then
264 FTU_control_State <= CONFIG_COUNTER;
265 elsif (wait_cntr = 1) then
266 prescaling_sig <= ram_doa;
267 FTU_control_State <= CONFIG_COUNTER;
268 prescaling_ready <= '1';
269 else
270 cntr_reset_sig <= '1';
271 ram_ada_sig <= (others => '0');
272 wait_cntr <= 0;
273 new_prescaling_in_RAM <= '0';
274 ram_ena_sig <= '0';
275 new_rates_busy <= '0';
276 prescaling_ready <= '0';
277 FTU_control_State <= RUNNING;
278 end if;
279
280 when CONFIG_ENABLE =>
281 ram_enable_cntr <= ram_enable_cntr + 1;
282 new_rates_busy <= '1';
283 if (ram_enable_cntr = 0) then
284 ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
285 FTU_control_State <= CONFIG_ENABLE;
286 elsif (ram_enable_cntr > 0 and ram_enable_cntr < NO_OF_ENABLE + 1) then
287 ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr + 1, RAM_ADDR_WIDTH_B);
288 enable_array_sig(ram_enable_cntr - 1) <= ram_dob;
289 enables_ready <= '1';
290 FTU_control_State <= CONFIG_ENABLE;
291 else
292 ram_adb_sig <= (others => '0');
293 ram_enable_cntr <= 0;
294 new_enables_in_RAM <= '0';
295 ram_enb_sig <= '0';
296 cntr_reset_sig <= '1';
297 new_rates_busy <= '0';
298 enables_ready <= '0';
299 FTU_control_State <= RUNNING;
300 end if;
301
302 when CONFIG_DAC =>
303 new_rates_busy <= '1';
304 if (ram_dac_cntr <= (NO_OF_DAC - NO_OF_DAC_NOT_USED + 2)) then
305 ram_dac_cntr <= ram_dac_cntr + 1;
306 if (ram_dac_cntr = 0) then
307 FTU_control_State <= CONFIG_DAC;
308 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);
309 elsif (ram_dac_cntr > 0 and ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then
310 dac_array_sig(ram_dac_cntr - 1) <= conv_integer(unsigned(ram_dob(11 downto 0)));
311 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);
312 FTU_control_State <= CONFIG_DAC;
313 elsif (ram_dac_cntr > 0 and ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED + 1)) then
314 dac_array_sig(ram_dac_cntr - 1 + NO_OF_DAC_NOT_USED) <= conv_integer(unsigned(ram_dob(11 downto 0)));
315 ram_adb_sig <= (others => '0');
316 FTU_control_State <= CONFIG_DAC;
317 DACs_ready <= '1';
318 else
319 ram_adb_sig <= (others => '0');
320 config_start_sig <= '1';
321 DACs_ready <= '0';
322 FTU_control_State <= CONFIG_DAC;
323 end if;
324 else
325 if (config_ready = '1') then
326 ram_dac_cntr <= 0;
327 new_DACs_in_RAM <= '0';
328 cntr_reset_sig <= '1';
329 new_rates_busy <= '0';
330 FTU_control_State <= RUNNING;
331 elsif (config_ready = '0' and config_started = '1') then
332 ram_enb_sig <= '0';
333 config_start_sig <= '0';
334 FTU_control_State <= CONFIG_DAC;
335 else
336 FTU_control_State <= CONFIG_DAC;
337 end if;
338 end if;
339
340 when WRITE_RATES => -- write trigger/patch rates to RAM B and overflow register to RAM A
341 new_rates_busy <= '1';
342 ram_counter_cntr <= ram_counter_cntr + 1;
343 if (ram_counter_cntr < NO_OF_COUNTER) then
344 ram_enb_sig <= '1';
345 ram_web_sig <= "1";
346 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr), RAM_ADDR_WIDTH_B);
347 ram_dib_sig <= conv_std_logic_vector(rate_array_sig(ram_counter_cntr), 16);
348 FTU_control_State <= WRITE_RATES;
349 elsif (ram_counter_cntr = NO_Of_COUNTER) then
350 ram_dib_sig <= (others => '0');
351 ram_adb_sig <= (others => '0');
352 ram_enb_sig <= '0';
353 ram_web_sig <= "0";
354 ram_ena_sig <= '1';
355 ram_wea_sig <= "1";
356 ram_ada_sig <= conv_std_logic_vector(NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1, RAM_ADDR_WIDTH_A);
357 ram_dia_sig <= overflow_array;
358 FTU_control_State <= WRITE_RATES;
359 else
360 ram_ena_sig <= '0';
361 ram_wea_sig <= "0";
362 ram_counter_cntr <= 0;
363 new_rates_busy <= '0';
364 FTU_control_State <= RUNNING;
365 end if;
366
367 when WRITE_DAC => -- write new DAC values from RS485 to RAM
368 ram_dac_cntr <= ram_dac_cntr + 1;
369 if (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)) then
370 ram_enb_sig <= '1';
371 ram_web_sig <= "1";
372 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr), RAM_ADDR_WIDTH_B);
373 ram_dib_sig <= conv_std_logic_vector(dac_array_rs485_out(ram_dac_cntr), 16);
374 FTU_control_State <= WRITE_DAC;
375 elsif (ram_dac_cntr = (NO_OF_DAC - NO_OF_DAC_NOT_USED - 1)) then
376 ram_enb_sig <= '1';
377 ram_web_sig <= "1";
378 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr), RAM_ADDR_WIDTH_B);
379 ram_dib_sig <= conv_std_logic_vector(dac_array_rs485_out(ram_dac_cntr + NO_OF_DAC_NOT_USED), 16);
380 FTU_control_State <= WRITE_DAC;
381 else
382 ram_enb_sig <= '0';
383 ram_web_sig <= "0";
384 new_DACs_in_RAM <= '1';
385 ram_dib_sig <= (others => '0');
386 ram_adb_sig <= (others => '0');
387 ram_dac_cntr <= 0;
388 FTU_control_State <= RUNNING;
389 end if;
390
391 when WRITE_ENABLE => -- write new enable patterns from RS485 to RAM
392 ram_enable_cntr <= ram_enable_cntr + 1;
393 if (ram_enable_cntr < NO_OF_ENABLE) then
394 ram_enb_sig <= '1';
395 ram_web_sig <= "1";
396 ram_adb_sig <= conv_std_logic_vector(ram_enable_cntr, RAM_ADDR_WIDTH_B);
397 ram_dib_sig <= enable_array_rs485_out(ram_enable_cntr);
398 else
399 ram_enb_sig <= '0';
400 ram_web_sig <= "0";
401 new_enables_in_RAM <= '1';
402 ram_dib_sig <= (others => '0');
403 ram_adb_sig <= (others => '0');
404 ram_enable_cntr <= 0;
405 FTU_control_State <= RUNNING;
406 end if;
407
408 when WRITE_PRESCALING => -- write new prescaling from RS485 to RAM
409 wait_cntr <= wait_cntr + 1;
410 if (wait_cntr = 0) then
411 ram_ena_sig <= '1';
412 ram_wea_sig <= "1";
413 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO), RAM_ADDR_WIDTH_A);
414 ram_dia_sig <= prescaling_rs485_out;
415 else
416 ram_ena_sig <= '0';
417 ram_wea_sig <= "0";
418 new_prescaling_in_RAM <= '1';
419 ram_dia_sig <= (others => '0');
420 ram_ada_sig <= (others => '0');
421 wait_cntr <= 0;
422 FTU_control_State <= RUNNING;
423 end if;
424
425 when READOUT_RATES => -- read most recent rate values from RAM and send them to RS485 module
426 ram_counter_cntr <= ram_counter_cntr + 1;
427 if (ram_counter_cntr = 0) then
428 ram_enb_sig <= '1';
429 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr + 1), RAM_ADDR_WIDTH_B);
430 FTU_control_State <= READOUT_RATES;
431 elsif (ram_counter_cntr < NO_OF_COUNTER) then
432 ram_ena_sig <= '1';
433 ram_ada_sig <= conv_std_logic_vector(((NO_OF_ENABLE + NO_OF_COUNTER + NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1), RAM_ADDR_WIDTH_A);
434 ram_enb_sig <= '1';
435 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + ram_counter_cntr + 1), RAM_ADDR_WIDTH_B);
436 rate_array_rs485(ram_counter_cntr - 1) <= conv_integer(unsigned(ram_dob));
437 FTU_control_State <= READOUT_RATES;
438 elsif (ram_counter_cntr = NO_Of_COUNTER) then
439 ram_enb_sig <= '0';
440 ram_adb_sig <= (others => '0');
441 rate_array_rs485(ram_counter_cntr - 1) <= conv_integer(unsigned(ram_dob));
442 ram_ena_sig <= '1';
443 ram_ada_sig <= conv_std_logic_vector(((NO_OF_ENABLE + NO_OF_COUNTER + NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO + 1), RAM_ADDR_WIDTH_A);
444 FTU_control_State <= READOUT_RATES;
445 elsif (ram_counter_cntr = NO_Of_COUNTER + 1) then
446 ram_enb_sig <= '0';
447 ram_adb_sig <= (others => '0');
448 ram_ena_sig <= '0';
449 ram_ada_sig <= (others => '0');
450 overflow_array_rs485_in <= ram_doa;
451 rates_ready <= '1';
452 FTU_control_State <= READOUT_RATES;
453 else
454 ram_enb_sig <= '0';
455 ram_adb_sig <= (others => '0');
456 ram_ena_sig <= '0';
457 ram_ada_sig <= (others => '0');
458 ram_counter_cntr <= 0;
459 rates_ready <= '0';
460 FTU_control_State <= RUNNING;
461 end if;
462
463 when READOUT_DAC => -- read most recent DAC values from RAM and send them to RS485 module
464 ram_dac_cntr <= ram_dac_cntr + 1;
465 if (ram_dac_cntr = 0) then
466 ram_enb_sig <= '1';
467 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);
468 FTU_control_State <= READOUT_DAC;
469 elsif (ram_dac_cntr < (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then
470 ram_enb_sig <= '1';
471 ram_adb_sig <= conv_std_logic_vector((NO_OF_ENABLE + NO_OF_COUNTER + ram_dac_cntr + 1), RAM_ADDR_WIDTH_B);
472 dac_array_sig(ram_dac_cntr - 1) <= conv_integer(unsigned(ram_dob(11 downto 0)));
473 FTU_control_State <= READOUT_DAC;
474 elsif (ram_dac_cntr = (NO_OF_DAC - NO_OF_DAC_NOT_USED)) then
475 ram_enb_sig <= '0';
476 ram_adb_sig <= (others => '0');
477 dac_array_sig(ram_dac_cntr + NO_OF_DAC_NOT_USED - 1) <= conv_integer(unsigned(ram_dob(11 downto 0)));
478 DACs_ready <= '1';
479 FTU_control_State <= READOUT_DAC;
480 else
481 ram_enb_sig <= '0';
482 ram_adb_sig <= (others => '0');
483 DACs_ready <= '0';
484 ram_dac_cntr <= 0;
485 FTU_control_State <= RUNNING;
486 end if;
487
488 when READOUT_ENABLE => -- read most recent enable patterns from RAM and send them to RS485 module
489 ram_enable_cntr <= ram_enable_cntr + 1;
490 if (ram_enable_cntr = 0) then
491 ram_enb_sig <= '1';
492 ram_adb_sig <= conv_std_logic_vector((ram_enable_cntr + 1), RAM_ADDR_WIDTH_B);
493 FTU_control_State <= READOUT_ENABLE;
494 elsif (ram_enable_cntr < NO_OF_ENABLE) then
495 ram_enb_sig <= '1';
496 ram_adb_sig <= conv_std_logic_vector((ram_enable_cntr + 1), RAM_ADDR_WIDTH_B);
497 enable_array_sig(ram_enable_cntr - 1) <= ram_dob;
498 FTU_control_State <= READOUT_ENABLE;
499 elsif (ram_enable_cntr = NO_OF_ENABLE) then
500 ram_enb_sig <= '0';
501 ram_adb_sig <= (others => '0');
502 enable_array_sig(ram_enable_cntr - 1) <= ram_dob;
503 enables_ready <= '1';
504 FTU_control_State <= READOUT_ENABLE;
505 else
506 ram_enb_sig <= '0';
507 ram_adb_sig <= (others => '0');
508 enables_ready <= '0';
509 ram_enable_cntr <= 0;
510 FTU_control_State <= RUNNING;
511 end if;
512
513 when READOUT_PRESCALING => -- read most recent prescaling value from RAM and send it to RS485 module
514 wait_cntr <= wait_cntr + 1;
515 if (wait_cntr = 0) then
516 ram_ena_sig <= '1';
517 ram_ada_sig <= conv_std_logic_vector((NO_OF_ENABLE*RAM_ADDR_RATIO + NO_OF_COUNTER*RAM_ADDR_RATIO + (NO_OF_DAC - NO_OF_DAC_NOT_USED)*RAM_ADDR_RATIO) + 1, RAM_ADDR_WIDTH_A);
518 FTU_control_State <= READOUT_PRESCALING;
519 elsif (wait_cntr = 1) then
520 ram_ena_sig <= '1';
521 ram_ada_sig <= (others => '0');
522 prescaling_sig <= ram_doa;
523 FTU_control_State <= READOUT_PRESCALING;
524 elsif (wait_cntr = 2) then
525 ram_ena_sig <= '0';
526 ram_ada_sig <= (others => '0');
527 overflow_array_rs485_in <= ram_doa;
528 prescaling_ready <= '1';
529 FTU_control_State <= READOUT_PRESCALING;
530 else
531 ram_ena_sig <= '0';
532 ram_ada_sig <= (others => '0');
533 prescaling_ready <= '0';
534 wait_cntr <= 0;
535 FTU_control_State <= RUNNING;
536 end if;
537
538 end case;
539 end if;
540 end process FTU_control_FSM;
541
542 detect_new_rates: process(new_rates, new_rates_busy)
543 begin
544 if(new_rates_busy = '1') then
545 new_rates_sig <= '0';
546 elsif rising_edge(new_rates) then
547 new_rates_sig <= '1';
548 end if;
549 end process detect_new_rates;
550
551 reset <= reset_sig;
552
553 config_start <= config_start_sig;
554 dac_array <= dac_array_sig;
555
556 enable_array <= enable_array_sig;
557 prescaling <= prescaling_sig;
558
559 rate_array_sig <= rate_array;
560 cntr_reset <= cntr_reset_sig;
561
562 ram_ena <= ram_ena_sig;
563 ram_enb <= ram_enb_sig;
564 ram_wea <= ram_wea_sig;
565 ram_web <= ram_web_sig;
566 ram_ada <= ram_ada_sig;
567 ram_adb <= ram_adb_sig;
568 ram_dia <= ram_dia_sig;
569 ram_dib <= ram_dib_sig;
570
571end Behavioral;
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