source: firmware/FTU/FTU_top.vhd@ 10047

Last change on this file since 10047 was 10037, checked in by weitzel, 14 years ago
FTU counter changed from 16 to 30 bit
File size: 20.3 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 11:59:40 01/19/2010
6-- Design Name:
7-- Module Name: FTU_top - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Top level entity of FACT FTU board
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Revision 0.02 - New design of FTU firmware, 12.07.2010, Q. Weitzel
18-- Revision 0.03 - counters changed from 16 to 30 bit, 19.10.2010, Q. Weitzel
19-- Additional Comments:
20--
21----------------------------------------------------------------------------------
22
23library IEEE;
24use IEEE.STD_LOGIC_1164.ALL;
25use IEEE.STD_LOGIC_ARITH.ALL;
26use IEEE.STD_LOGIC_UNSIGNED.ALL;
27
28library ftu_definitions;
29USE ftu_definitions.ftu_array_types.all;
30USE ftu_definitions.ftu_constants.all;
31
32---- Uncomment the following library declaration if instantiating
33---- any Xilinx primitives in this code.
34library UNISIM;
35use UNISIM.VComponents.all;
36
37entity FTU_top is
38 port(
39 -- global control
40 ext_clk : IN STD_LOGIC; -- external clock from FTU board
41 brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address
42 --brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID
43
44 -- rate counters LVDS inputs
45 -- use IBUFDS differential input buffer
46 patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch
47 patch_A_n : IN STD_LOGIC;
48 patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch
49 patch_B_n : IN STD_LOGIC;
50 patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch
51 patch_C_n : IN STD_LOGIC;
52 patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch
53 patch_D_n : IN STD_LOGIC;
54 trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit
55 trig_prim_n : IN STD_LOGIC;
56
57 -- DAC interface
58 sck : OUT STD_LOGIC; -- serial clock to DAC
59 mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in
60 clr : OUT STD_LOGIC; -- clear signal to DAC
61 cs_ld : OUT STD_LOGIC; -- chip select or load to DAC
62
63 -- RS-485 interface to FTM
64 rx : IN STD_LOGIC; -- serial data from FTM
65 tx : OUT STD_LOGIC; -- serial data to FTM
66 rx_en : OUT STD_LOGIC; -- enable RS-485 receiver
67 tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter
68
69 -- analog buffer enable
70 enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
71 enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
72 enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
73 enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
74
75 -- testpoints
76 TP_A : OUT STD_LOGIC_VECTOR(11 downto 0) -- testpoints
77 );
78end FTU_top;
79
80architecture Behavioral of FTU_top is
81
82 signal reset_sig : STD_LOGIC; -- initialized in FTU_control
83
84 --single-ended trigger signals for rate counter
85 signal patch_A_sig : STD_LOGIC := '0';
86 signal patch_B_sig : STD_LOGIC := '0';
87 signal patch_C_sig : STD_LOGIC := '0';
88 signal patch_D_sig : STD_LOGIC := '0';
89 signal trigger_sig : STD_LOGIC := '0';
90
91 --DAC/SPI interface
92 signal config_start_sig : STD_LOGIC; -- initialized in FTU_control
93 signal config_started_sig : STD_LOGIC; -- initialized in spi_interface
94 signal config_ready_sig : STD_LOGIC; -- initialized in spi_interface
95 signal dac_array_sig : dac_array_type; -- initialized in FTU_control
96
97 signal enable_array_sig : enable_array_type; -- initialized in FTU_control
98
99 --rate counter signals
100 signal cntr_reset_sig : STD_LOGIC; -- initialized in FTU_control
101 signal rate_array_sig : rate_array_type; -- initialized by counters
102 signal prescaling_sig : STD_LOGIC_VECTOR(7 downto 0); -- initialized in FTU_control
103 signal overflow_array : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
104 signal new_rate_A_sig : STD_LOGIC; -- initialized by patch A counter
105 signal new_rate_B_sig : STD_LOGIC; -- initialized by patch B counter
106 signal new_rate_C_sig : STD_LOGIC; -- initialized by patch C counter
107 signal new_rate_D_sig : STD_LOGIC; -- initialized by patch D counter
108 signal new_rate_t_sig : STD_LOGIC; -- initialized by trigger counter
109 signal new_rates_sig : STD_LOGIC := '0';
110
111 --attribute clock_signal : string;
112 --attribute clock_signal of new_rates_sig : signal is "no";
113
114 signal clk_50M_sig : STD_LOGIC; -- generated by internal DCM
115 signal clk_1M_sig : STD_LOGIC; -- generated from 50M clock by divider
116 signal clk_ready_sig : STD_LOGIC := '0'; -- set high by FTU_clk_gen when DCMs have locked
117
118 --signals for RAM control, all initialized in FTU_control
119 signal ram_ena_sig : STD_LOGIC;
120 signal ram_enb_sig : STD_LOGIC;
121 signal ram_wea_sig : STD_LOGIC_VECTOR(0 downto 0);
122 signal ram_web_sig : STD_LOGIC_VECTOR(0 downto 0);
123 signal ram_ada_sig : STD_LOGIC_VECTOR(5 downto 0);
124 signal ram_adb_sig : STD_LOGIC_VECTOR(4 downto 0);
125 signal ram_dia_sig : STD_LOGIC_VECTOR(7 downto 0);
126 signal ram_dib_sig : STD_LOGIC_VECTOR(15 downto 0);
127 signal ram_doa_sig : STD_LOGIC_VECTOR(7 downto 0);
128 signal ram_dob_sig : STD_LOGIC_VECTOR(15 downto 0);
129
130 --signals from RS485 module, all initialized in FTU_rs485_control (or deeper)
131 signal new_DACs_sig : std_logic;
132 signal new_enables_sig : std_logic;
133 signal new_prescaling_sig : std_logic;
134 signal read_rates_sig : std_logic;
135 signal read_DACs_sig : std_logic;
136 signal read_enables_sig : std_logic;
137 signal read_prescaling_sig : std_logic;
138 signal ping_pong_sig : std_logic;
139 signal dac_array_rs485_out_sig : dac_array_type;
140 signal enable_array_rs485_out_sig : enable_array_type;
141 signal prescaling_rs485_out_sig : STD_LOGIC_VECTOR(7 downto 0);
142
143 --signals to RS485 module, all initialized in FTU_control
144 signal rates_ready_sig : std_logic;
145 signal DACs_ready_sig : std_logic;
146 signal enables_ready_sig : std_logic;
147 signal prescaling_ready_sig : std_logic;
148 signal ping_pong_ready_sig : std_logic;
149 signal rate_array_rs485_sig : rate_array_type;
150 signal overflow_array_rs485_in_sig : STD_LOGIC_VECTOR(7 downto 0);
151
152 --signals for FPGA DNA identifier
153 signal dna_sig : STD_LOGIC_VECTOR(63 downto 0); -- initialized in FTU_dna_gen
154 signal dna_start_sig : STD_LOGIC; -- initialized in FTU_control
155 signal dna_ready_sig : STD_LOGIC; -- initialized in FTU_dna_gen
156
157 component FTU_clk_gen
158 port(
159 clk : IN STD_LOGIC;
160 rst : IN STD_LOGIC;
161 clk_50 : OUT STD_LOGIC;
162 clk_1 : OUT STD_LOGIC;
163 ready : OUT STD_LOGIC
164 );
165 end component;
166
167 component FTU_rate_counter is
168 port(
169 clk : in std_logic;
170 cntr_reset : in std_logic;
171 trigger : in std_logic;
172 prescaling : in std_logic_vector(7 downto 0);
173 counts : out integer range 0 to 2**30 - 1;
174 overflow : out std_logic;
175 new_rate : out std_logic
176 );
177 end component;
178
179 component FTU_control -- comments: see entity file
180 port(
181 clk_50MHz : IN std_logic;
182 clk_ready : IN std_logic;
183 config_started : IN std_logic;
184 config_ready : IN std_logic;
185 ram_doa : IN STD_LOGIC_VECTOR(7 downto 0);
186 ram_dob : IN STD_LOGIC_VECTOR(15 downto 0);
187 rate_array : IN rate_array_type;
188 overflow_array : in STD_LOGIC_VECTOR(7 downto 0);
189 new_rates : IN std_logic;
190 new_DACs : IN std_logic;
191 new_enables : IN std_logic;
192 new_prescaling : IN std_logic;
193 read_rates : IN std_logic;
194 read_DACs : IN std_logic;
195 read_enables : IN std_logic;
196 read_prescaling : IN std_logic;
197 ping_pong : IN std_logic;
198 dac_array_rs485_out : IN dac_array_type;
199 enable_array_rs485_out : IN enable_array_type;
200 prescaling_rs485_out : IN STD_LOGIC_VECTOR(7 downto 0);
201 dna_ready : IN std_logic;
202 reset : OUT std_logic;
203 config_start : OUT std_logic;
204 ram_ena : OUT std_logic;
205 ram_enb : OUT std_logic;
206 ram_wea : OUT STD_LOGIC_VECTOR(0 downto 0);
207 ram_web : OUT STD_LOGIC_VECTOR(0 downto 0);
208 ram_ada : OUT STD_LOGIC_VECTOR(5 downto 0);
209 ram_adb : OUT STD_LOGIC_VECTOR(4 downto 0);
210 ram_dia : OUT STD_LOGIC_VECTOR(7 downto 0);
211 ram_dib : OUT STD_LOGIC_VECTOR(15 downto 0);
212 rate_array_rs485 : OUT rate_array_type;
213 overflow_array_rs485_in : OUT STD_LOGIC_VECTOR(7 downto 0);
214 rates_ready : OUT std_logic;
215 DACs_ready : OUT std_logic;
216 enables_ready : OUT std_logic;
217 prescaling_ready : OUT std_logic;
218 ping_pong_ready : OUT std_logic;
219 dac_array : OUT dac_array_type;
220 enable_array : OUT enable_array_type;
221 cntr_reset : OUT STD_LOGIC;
222 prescaling : OUT STD_LOGIC_VECTOR(7 downto 0);
223 dna_start : OUT std_logic
224 );
225 end component;
226
227 component FTU_spi_interface
228 port(
229 clk_50MHz : IN std_logic;
230 config_start : IN std_logic;
231 dac_array : IN dac_array_type;
232 config_ready : OUT std_logic;
233 config_started : OUT std_logic;
234 dac_cs : OUT std_logic;
235 mosi : OUT std_logic;
236 sclk : OUT std_logic
237 );
238 end component;
239
240 component FTU_rs485_control -- comments: see entity file
241 port(
242 main_clk : IN std_logic;
243 brd_add : IN std_logic_vector(5 downto 0);
244 rx_d : IN std_logic;
245 rates_ready : IN std_logic;
246 DACs_ready : IN std_logic;
247 enables_ready : IN std_logic;
248 prescaling_ready : IN std_logic;
249 ping_pong_ready : IN std_logic;
250 rate_array_rs485 : IN rate_array_type;
251 overflow_array_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0);
252 dac_array_rs485_in : IN dac_array_type;
253 enable_array_rs485_in : IN enable_array_type;
254 prescaling_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0);
255 dna : IN STD_LOGIC_VECTOR(63 downto 0);
256 rx_en : OUT std_logic;
257 tx_d : OUT std_logic;
258 tx_en : OUT std_logic;
259 new_DACs : OUT std_logic;
260 new_enables : OUT std_logic;
261 new_prescaling : OUT std_logic;
262 read_rates : OUT std_logic;
263 read_DACs : OUT std_logic;
264 read_enables : OUT std_logic;
265 read_prescaling : OUT std_logic;
266 ping_pong : OUT std_logic;
267 dac_array_rs485_out : OUT dac_array_type;
268 enable_array_rs485_out : OUT enable_array_type;
269 prescaling_rs485_out : OUT STD_LOGIC_VECTOR(7 downto 0)
270 );
271 end component;
272
273 component FTU_dna_gen
274 port(
275 clk : IN STD_LOGIC;
276 start : IN STD_LOGIC;
277 dna : OUT STD_LOGIC_VECTOR(63 downto 0);
278 ready : OUT STD_LOGIC
279 );
280 end component;
281
282 component FTU_dual_port_ram64
283 port(
284 clka : IN std_logic;
285 ena : IN std_logic;
286 wea : IN std_logic_VECTOR(0 downto 0);
287 addra : IN std_logic_VECTOR(5 downto 0);
288 dina : IN std_logic_VECTOR(7 downto 0);
289 douta : OUT std_logic_VECTOR(7 downto 0);
290 clkb : IN std_logic;
291 enb : IN std_logic;
292 web : IN std_logic_VECTOR(0 downto 0);
293 addrb : IN std_logic_VECTOR(4 downto 0);
294 dinb : IN std_logic_VECTOR(15 downto 0);
295 doutb : OUT std_logic_VECTOR(15 downto 0)
296 );
297 end component;
298
299 -- Synplicity black box declaration
300 attribute syn_black_box : boolean;
301 attribute syn_black_box of FTU_dual_port_ram64: component is true;
302 -- avoid "black box" warning during synthesis
303 attribute box_type : string;
304 attribute box_type of FTU_dual_port_ram64: component is "black_box";
305
306begin
307
308 clr <= '1';
309 TP_A <= "000000000000";
310
311 enables_A <= enable_array_sig(0)(8 downto 0);
312 enables_B <= enable_array_sig(1)(8 downto 0);
313 enables_C <= enable_array_sig(2)(8 downto 0);
314 enables_D <= enable_array_sig(3)(8 downto 0);
315
316 new_rates_sig <= new_rate_A_sig and new_rate_B_sig and new_rate_C_sig and new_rate_D_sig and new_rate_t_sig;
317
318 --these bits are not used, others come from rate counters
319 overflow_array(5) <= '0';
320 overflow_array(6) <= '0';
321 overflow_array(7) <= '0';
322
323 --differential input buffer for patch A
324 IBUFDS_LVDS_33_A : IBUFDS_LVDS_33
325 port map(
326 O => patch_A_sig,
327 I => patch_A_p,
328 IB => patch_A_n
329 );
330
331 --differential input buffer for patch B
332 IBUFDS_LVDS_33_B : IBUFDS_LVDS_33
333 port map(
334 O => patch_B_sig,
335 I => patch_B_p,
336 IB => patch_B_n
337 );
338
339 --differential input buffer for patch C
340 IBUFDS_LVDS_33_C : IBUFDS_LVDS_33
341 port map(
342 O => patch_C_sig,
343 I => patch_C_p,
344 IB => patch_C_n
345 );
346
347 --differential input buffer for patch D
348 IBUFDS_LVDS_33_D : IBUFDS_LVDS_33
349 port map(
350 O => patch_D_sig,
351 I => patch_D_p,
352 IB => patch_D_n
353 );
354
355 --differential input buffer for trigger
356 IBUFDS_LVDS_33_t : IBUFDS_LVDS_33
357 port map(
358 O => trigger_sig,
359 I => trig_prim_p,
360 IB => trig_prim_n
361 );
362
363 Inst_FTU_clk_gen : FTU_clk_gen
364 port map(
365 clk => ext_clk,
366 rst => reset_sig,
367 clk_50 => clk_50M_sig,
368 clk_1 => clk_1M_sig,
369 ready => clk_ready_sig
370 );
371
372 Inst_FTU_rate_counter_A : FTU_rate_counter
373 port map(
374 clk => clk_1M_sig,
375 cntr_reset => cntr_reset_sig,
376 trigger => patch_A_sig,
377 prescaling => prescaling_sig,
378 counts => rate_array_sig(0),
379 overflow => overflow_array(0),
380 new_rate => new_rate_A_sig
381 );
382
383 Inst_FTU_rate_counter_B : FTU_rate_counter
384 port map(
385 clk => clk_1M_sig,
386 cntr_reset => cntr_reset_sig,
387 trigger => patch_B_sig,
388 prescaling => prescaling_sig,
389 counts => rate_array_sig(1),
390 overflow => overflow_array(1),
391 new_rate => new_rate_B_sig
392 );
393
394 Inst_FTU_rate_counter_C : FTU_rate_counter
395 port map(
396 clk => clk_1M_sig,
397 cntr_reset => cntr_reset_sig,
398 trigger => patch_C_sig,
399 prescaling => prescaling_sig,
400 counts => rate_array_sig(2),
401 overflow => overflow_array(2),
402 new_rate => new_rate_C_sig
403 );
404
405 Inst_FTU_rate_counter_D : FTU_rate_counter
406 port map(
407 clk => clk_1M_sig,
408 cntr_reset => cntr_reset_sig,
409 trigger => patch_D_sig,
410 prescaling => prescaling_sig,
411 counts => rate_array_sig(3),
412 overflow => overflow_array(3),
413 new_rate => new_rate_D_sig
414 );
415
416 Inst_FTU_rate_counter_t : FTU_rate_counter
417 port map(
418 clk => clk_1M_sig,
419 cntr_reset => cntr_reset_sig,
420 trigger => trigger_sig,
421 prescaling => prescaling_sig,
422 counts => rate_array_sig(4),
423 overflow => overflow_array(4),
424 new_rate => new_rate_t_sig
425 );
426
427 Inst_FTU_control : FTU_control
428 port map(
429 clk_50MHz => clk_50M_sig,
430 clk_ready => clk_ready_sig,
431 config_started => config_started_sig,
432 config_ready => config_ready_sig,
433 ram_doa => ram_doa_sig,
434 ram_dob => ram_dob_sig,
435 rate_array => rate_array_sig,
436 overflow_array => overflow_array,
437 new_rates => new_rates_sig,
438 new_DACs => new_DACs_sig,
439 new_enables => new_enables_sig,
440 new_prescaling => new_prescaling_sig,
441 read_rates => read_rates_sig,
442 read_DACs => read_DACs_sig,
443 read_enables => read_enables_sig,
444 read_prescaling => read_prescaling_sig,
445 ping_pong => ping_pong_sig,
446 dac_array_rs485_out => dac_array_rs485_out_sig,
447 enable_array_rs485_out => enable_array_rs485_out_sig,
448 prescaling_rs485_out => prescaling_rs485_out_sig,
449 dna_ready => dna_ready_sig,
450 reset => reset_sig,
451 config_start => config_start_sig,
452 ram_ena => ram_ena_sig,
453 ram_enb => ram_enb_sig,
454 ram_wea => ram_wea_sig,
455 ram_web => ram_web_sig,
456 ram_ada => ram_ada_sig,
457 ram_adb => ram_adb_sig,
458 ram_dia => ram_dia_sig,
459 ram_dib => ram_dib_sig,
460 rate_array_rs485 => rate_array_rs485_sig,
461 overflow_array_rs485_in => overflow_array_rs485_in_sig,
462 rates_ready => rates_ready_sig,
463 DACs_ready => DACs_ready_sig,
464 enables_ready => enables_ready_sig,
465 prescaling_ready => prescaling_ready_sig,
466 ping_pong_ready => ping_pong_ready_sig,
467 dac_array => dac_array_sig,
468 enable_array => enable_array_sig,
469 cntr_reset => cntr_reset_sig,
470 prescaling => prescaling_sig,
471 dna_start => dna_start_sig
472 );
473
474 Inst_FTU_spi_interface : FTU_spi_interface
475 port map(
476 clk_50MHz => clk_50M_sig,
477 config_start => config_start_sig,
478 dac_array => dac_array_sig,
479 config_ready => config_ready_sig,
480 config_started => config_started_sig,
481 dac_cs => cs_ld,
482 mosi => mosi,
483 sclk => sck
484 );
485
486 Inst_FTU_rs485_control : FTU_rs485_control
487 port map(
488 main_clk => clk_50M_sig,
489 brd_add => brd_add,
490 rx_d => rx,
491 rates_ready => rates_ready_sig,
492 DACs_ready => DACs_ready_sig,
493 enables_ready => enables_ready_sig,
494 prescaling_ready => prescaling_ready_sig,
495 ping_pong_ready => ping_pong_ready_sig,
496 rate_array_rs485 => rate_array_rs485_sig,
497 overflow_array_rs485_in => overflow_array_rs485_in_sig,
498 dac_array_rs485_in => dac_array_sig,
499 enable_array_rs485_in => enable_array_sig,
500 prescaling_rs485_in => prescaling_sig,
501 dna => dna_sig,
502 rx_en => rx_en,
503 tx_d => tx,
504 tx_en => tx_en,
505 new_DACs => new_DACs_sig,
506 new_enables => new_enables_sig,
507 new_prescaling => new_prescaling_sig,
508 read_rates => read_rates_sig,
509 read_DACs => read_DACs_sig,
510 read_enables => read_enables_sig,
511 read_prescaling => read_prescaling_sig,
512 ping_pong => ping_pong_sig,
513 dac_array_rs485_out => dac_array_rs485_out_sig,
514 enable_array_rs485_out => enable_array_rs485_out_sig,
515 prescaling_rs485_out => prescaling_rs485_out_sig
516 );
517
518 Inst_FTU_dna_gen : FTU_dna_gen
519 port map(
520 clk => clk_50M_sig,
521 start => dna_start_sig,
522 dna => dna_sig,
523 ready => dna_ready_sig
524 );
525
526 Inst_FTU_dual_port_ram64 : FTU_dual_port_ram64
527 port map(
528 clka => clk_50M_sig,
529 ena => ram_ena_sig,
530 wea => ram_wea_sig,
531 addra => ram_ada_sig,
532 dina => ram_dia_sig,
533 douta => ram_doa_sig,
534 clkb => clk_50M_sig,
535 enb => ram_enb_sig,
536 web => ram_web_sig,
537 addrb => ram_adb_sig,
538 dinb => ram_dib_sig,
539 doutb => ram_dob_sig
540 );
541
542end Behavioral;
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