source: firmware/FTU/FTU_top.vhd@ 9880

Last change on this file since 9880 was 9880, checked in by weitzel, 15 years ago
FTU_rate_counter added and FTU_control state machine extended
File size: 11.8 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 11:59:40 01/19/2010
6-- Design Name:
7-- Module Name: FTU_top - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Top level entity of FACT FTU board
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Revision 0.02 - New design of FTU firmware, 12.07.2010, Q. Weitzel
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21
22library IEEE;
23use IEEE.STD_LOGIC_1164.ALL;
24use IEEE.STD_LOGIC_ARITH.ALL;
25use IEEE.STD_LOGIC_UNSIGNED.ALL;
26
27library ftu_definitions;
28USE ftu_definitions.ftu_array_types.all;
29
30---- Uncomment the following library declaration if instantiating
31---- any Xilinx primitives in this code.
32library UNISIM;
33use UNISIM.VComponents.all;
34
35entity FTU_top is
36 port(
37 -- global control
38 ext_clk : IN STD_LOGIC; -- external clock from FTU board
39 brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address
40 brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID
41
42 -- rate counters LVDS inputs
43 -- use IBUFDS differential input buffer
44 patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch
45 patch_A_n : IN STD_LOGIC;
46 patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch
47 patch_B_n : IN STD_LOGIC;
48 patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch
49 patch_C_n : IN STD_LOGIC;
50 patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch
51 patch_D_n : IN STD_LOGIC;
52 trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit
53 trig_prim_n : IN STD_LOGIC;
54
55 -- DAC interface
56 sck : OUT STD_LOGIC; -- serial clock to DAC
57 mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in
58 clr : OUT STD_LOGIC; -- clear signal to DAC
59 cs_ld : OUT STD_LOGIC; -- chip select or load to DAC
60
61 -- RS-485 interface to FTM
62 rx : IN STD_LOGIC; -- serial data from FTM
63 tx : OUT STD_LOGIC; -- serial data to FTM
64 rx_en : OUT STD_LOGIC; -- enable RS-485 receiver
65 tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter
66
67 -- analog buffer enable
68 enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
69 enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
70 enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
71 enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
72
73 -- testpoints
74 TP_A : OUT STD_LOGIC_VECTOR(11 downto 0) -- testpoints
75 );
76end FTU_top;
77
78architecture Behavioral of FTU_top is
79
80 signal reset_sig : STD_LOGIC; -- initialized in FTU_control
81 signal dac_clr_sig : STD_LOGIC := '1'; -- not used in hardware, initialize to 1 at power up
82
83 --single-ended trigger signals for rate counter
84 signal patch_A_sig : STD_LOGIC := '0';
85 signal patch_B_sig : STD_LOGIC := '0';
86 signal patch_C_sig : STD_LOGIC := '0';
87 signal patch_D_sig : STD_LOGIC := '0';
88 signal trigger_sig : STD_LOGIC := '0';
89
90 --DAC/SPI interface
91 signal config_start_sig : STD_LOGIC; -- initialized in FTU_control
92 signal config_started_sig : STD_LOGIC; -- initialized in spi_interface
93 signal config_ready_sig : STD_LOGIC; -- initialized in spi_interface
94 signal dac_array_sig : dac_array_type; -- initialized in FTU_control
95
96 signal enable_array_sig : enable_array_type; -- initialized in FTU_control
97
98 --rate counter signals
99 signal cntr_reset_sig : STD_LOGIC; -- initialized in FTU_control
100 signal rate_array_sig : rate_array_type := (0,0,0,0,0);
101 signal prescaling_sig : STD_LOGIC_VECTOR(7 downto 0);
102 signal overflow_array : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
103
104 signal clk_50M_sig : STD_LOGIC; -- generated by internal DCM
105 signal clk_ready_sig : STD_LOGIC := '0'; -- set high by FTU_clk_gen when DCMs have locked
106
107 --signals for RAM control, all initialized in FTU_control
108 signal ram_ena_sig : STD_LOGIC;
109 signal ram_enb_sig : STD_LOGIC;
110 signal ram_wea_sig : STD_LOGIC_VECTOR(0 downto 0);
111 signal ram_web_sig : STD_LOGIC_VECTOR(0 downto 0);
112 signal ram_ada_sig : STD_LOGIC_VECTOR(4 downto 0);
113 signal ram_adb_sig : STD_LOGIC_VECTOR(3 downto 0);
114 signal ram_dia_sig : STD_LOGIC_VECTOR(7 downto 0);
115 signal ram_dib_sig : STD_LOGIC_VECTOR(15 downto 0);
116 signal ram_doa_sig : STD_LOGIC_VECTOR(7 downto 0);
117 signal ram_dob_sig : STD_LOGIC_VECTOR(15 downto 0);
118
119 component FTU_clk_gen
120 port(
121 clk : IN STD_LOGIC;
122 rst : IN STD_LOGIC;
123 clk_50 : OUT STD_LOGIC;
124 ready : OUT STD_LOGIC
125 );
126 end component;
127
128 component FTU_rate_counter is
129 port(
130 clk : in std_logic;
131 cntr_reset : in std_logic;
132 trigger : in std_logic;
133 prescaling : in std_logic_vector(7 downto 0);
134 counts : out integer range 0 to 2**16 - 1;
135 overflow : out std_logic
136 );
137 end component;
138
139 component FTU_control
140 port(
141 clk_50MHz : IN std_logic;
142 clk_ready : IN std_logic;
143 config_started : IN std_logic;
144 config_ready : IN std_logic;
145 ram_doa : IN STD_LOGIC_VECTOR(7 downto 0);
146 ram_dob : IN STD_LOGIC_VECTOR(15 downto 0);
147 rate_array : IN rate_array_type;
148 reset : OUT std_logic;
149 config_start : OUT std_logic;
150 ram_ena : OUT std_logic;
151 ram_enb : OUT std_logic;
152 ram_wea : OUT STD_LOGIC_VECTOR(0 downto 0);
153 ram_web : OUT STD_LOGIC_VECTOR(0 downto 0);
154 ram_ada : OUT STD_LOGIC_VECTOR(4 downto 0);
155 ram_adb : OUT STD_LOGIC_VECTOR(3 downto 0);
156 ram_dia : OUT STD_LOGIC_VECTOR(7 downto 0);
157 ram_dib : OUT STD_LOGIC_VECTOR(15 downto 0);
158 dac_array : OUT dac_array_type;
159 enable_array : OUT enable_array_type;
160 cntr_reset : OUT STD_LOGIC;
161 prescaling : OUT STD_LOGIC_VECTOR(7 downto 0)
162 );
163 end component;
164
165 component FTU_spi_interface
166 port(
167 clk_50MHz : IN std_logic;
168 config_start : IN std_logic;
169 dac_array : IN dac_array_type;
170 config_ready : OUT std_logic;
171 config_started : OUT std_logic;
172 dac_cs : OUT std_logic;
173 mosi : OUT std_logic;
174 sclk : OUT std_logic
175 );
176 end component;
177
178 component FTU_dual_port_ram
179 port(
180 clka : IN std_logic;
181 ena : IN std_logic;
182 wea : IN std_logic_VECTOR(0 downto 0);
183 addra : IN std_logic_VECTOR(4 downto 0);
184 dina : IN std_logic_VECTOR(7 downto 0);
185 douta : OUT std_logic_VECTOR(7 downto 0);
186 clkb : IN std_logic;
187 enb : IN std_logic;
188 web : IN std_logic_VECTOR(0 downto 0);
189 addrb : IN std_logic_VECTOR(3 downto 0);
190 dinb : IN std_logic_VECTOR(15 downto 0);
191 doutb : OUT std_logic_VECTOR(15 downto 0)
192 );
193 end component;
194
195 -- Synplicity black box declaration
196 attribute syn_black_box : boolean;
197 attribute syn_black_box of FTU_dual_port_ram: component is true;
198
199begin
200
201 clr <= dac_clr_sig;
202
203 enables_A <= enable_array_sig(0)(8 downto 0);
204 enables_B <= enable_array_sig(1)(8 downto 0);
205 enables_C <= enable_array_sig(2)(8 downto 0);
206 enables_D <= enable_array_sig(3)(8 downto 0);
207
208 --differential input buffer for patch A
209 IBUFDS_LVDS_33_A : IBUFDS_LVDS_33
210 port map(
211 O => patch_A_sig,
212 I => patch_A_p,
213 IB => patch_A_n
214 );
215
216 --differential input buffer for patch B
217 IBUFDS_LVDS_33_B : IBUFDS_LVDS_33
218 port map(
219 O => patch_B_sig,
220 I => patch_B_p,
221 IB => patch_B_n
222 );
223
224 --differential input buffer for patch C
225 IBUFDS_LVDS_33_C : IBUFDS_LVDS_33
226 port map(
227 O => patch_C_sig,
228 I => patch_C_p,
229 IB => patch_C_n
230 );
231
232 --differential input buffer for patch D
233 IBUFDS_LVDS_33_D : IBUFDS_LVDS_33
234 port map(
235 O => patch_D_sig,
236 I => patch_D_p,
237 IB => patch_D_n
238 );
239
240 --differential input buffer for trigger
241 IBUFDS_LVDS_33_t : IBUFDS_LVDS_33
242 port map(
243 O => trigger_sig,
244 I => trig_prim_p,
245 IB => trig_prim_n
246 );
247
248 Inst_FTU_clk_gen : FTU_clk_gen
249 port map(
250 clk => ext_clk,
251 rst => reset_sig,
252 clk_50 => clk_50M_sig,
253 ready => clk_ready_sig
254 );
255
256 Inst_FTU_rate_counter_A : FTU_rate_counter
257 port map(
258 clk => clk_50M_sig,
259 cntr_reset => cntr_reset_sig,
260 trigger => patch_A_sig,
261 prescaling => prescaling_sig,
262 counts => rate_array_sig(0),
263 overflow => overflow_array(0)
264 );
265
266 Inst_FTU_rate_counter_B : FTU_rate_counter
267 port map(
268 clk => clk_50M_sig,
269 cntr_reset => cntr_reset_sig,
270 trigger => patch_B_sig,
271 prescaling => prescaling_sig,
272 counts => rate_array_sig(1),
273 overflow => overflow_array(1)
274 );
275
276 Inst_FTU_rate_counter_C : FTU_rate_counter
277 port map(
278 clk => clk_50M_sig,
279 cntr_reset => cntr_reset_sig,
280 trigger => patch_C_sig,
281 prescaling => prescaling_sig,
282 counts => rate_array_sig(2),
283 overflow => overflow_array(2)
284 );
285
286 Inst_FTU_rate_counter_D : FTU_rate_counter
287 port map(
288 clk => clk_50M_sig,
289 cntr_reset => cntr_reset_sig,
290 trigger => patch_D_sig,
291 prescaling => prescaling_sig,
292 counts => rate_array_sig(3),
293 overflow => overflow_array(3)
294 );
295
296 Inst_FTU_rate_counter_t : FTU_rate_counter
297 port map(
298 clk => clk_50M_sig,
299 cntr_reset => cntr_reset_sig,
300 trigger => trigger_sig,
301 prescaling => prescaling_sig,
302 counts => rate_array_sig(4),
303 overflow => overflow_array(4)
304 );
305
306 Inst_FTU_control : FTU_control
307 port map(
308 clk_50MHz => clk_50M_sig,
309 clk_ready => clk_ready_sig,
310 config_started => config_started_sig,
311 config_ready => config_ready_sig,
312 ram_doa => ram_doa_sig,
313 ram_dob => ram_dob_sig,
314 rate_array => rate_array_sig,
315 reset => reset_sig,
316 config_start => config_start_sig,
317 ram_ena => ram_ena_sig,
318 ram_enb => ram_enb_sig,
319 ram_wea => ram_wea_sig,
320 ram_web => ram_web_sig,
321 ram_ada => ram_ada_sig,
322 ram_adb => ram_adb_sig,
323 ram_dia => ram_dia_sig,
324 ram_dib => ram_dib_sig,
325 dac_array => dac_array_sig,
326 enable_array => enable_array_sig,
327 cntr_reset => cntr_reset_sig,
328 prescaling => prescaling_sig
329 );
330
331 Inst_FTU_spi_interface : FTU_spi_interface
332 port map(
333 clk_50MHz => clk_50M_sig,
334 config_start => config_start_sig,
335 dac_array => dac_array_sig,
336 config_ready => config_ready_sig,
337 config_started => config_started_sig,
338 dac_cs => cs_ld,
339 mosi => mosi,
340 sclk => sck
341 );
342
343 Inst_FTU_dual_port_ram : FTU_dual_port_ram
344 port map(
345 clka => clk_50M_sig,
346 ena => ram_ena_sig,
347 wea => ram_wea_sig,
348 addra => ram_ada_sig,
349 dina => ram_dia_sig,
350 douta => ram_doa_sig,
351 clkb => clk_50M_sig,
352 enb => ram_enb_sig,
353 web => ram_web_sig,
354 addrb => ram_adb_sig,
355 dinb => ram_dib_sig,
356 doutb => ram_dob_sig
357 );
358
359end Behavioral;
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