source: firmware/FTU/FTU_top.vhd@ 9890

Last change on this file since 9890 was 9890, checked in by weitzel, 15 years ago
overflow register implemented for FTU rate counter
File size: 12.7 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 11:59:40 01/19/2010
6-- Design Name:
7-- Module Name: FTU_top - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Top level entity of FACT FTU board
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Revision 0.02 - New design of FTU firmware, 12.07.2010, Q. Weitzel
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21
22library IEEE;
23use IEEE.STD_LOGIC_1164.ALL;
24use IEEE.STD_LOGIC_ARITH.ALL;
25use IEEE.STD_LOGIC_UNSIGNED.ALL;
26
27library ftu_definitions;
28USE ftu_definitions.ftu_array_types.all;
29
30---- Uncomment the following library declaration if instantiating
31---- any Xilinx primitives in this code.
32library UNISIM;
33use UNISIM.VComponents.all;
34
35entity FTU_top is
36 port(
37 -- global control
38 ext_clk : IN STD_LOGIC; -- external clock from FTU board
39 brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address
40 brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID
41
42 -- rate counters LVDS inputs
43 -- use IBUFDS differential input buffer
44 patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch
45 patch_A_n : IN STD_LOGIC;
46 patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch
47 patch_B_n : IN STD_LOGIC;
48 patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch
49 patch_C_n : IN STD_LOGIC;
50 patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch
51 patch_D_n : IN STD_LOGIC;
52 trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit
53 trig_prim_n : IN STD_LOGIC;
54
55 -- DAC interface
56 sck : OUT STD_LOGIC; -- serial clock to DAC
57 mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in
58 clr : OUT STD_LOGIC; -- clear signal to DAC
59 cs_ld : OUT STD_LOGIC; -- chip select or load to DAC
60
61 -- RS-485 interface to FTM
62 rx : IN STD_LOGIC; -- serial data from FTM
63 tx : OUT STD_LOGIC; -- serial data to FTM
64 rx_en : OUT STD_LOGIC; -- enable RS-485 receiver
65 tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter
66
67 -- analog buffer enable
68 enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
69 enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
70 enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
71 enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
72
73 -- testpoints
74 TP_A : OUT STD_LOGIC_VECTOR(11 downto 0) -- testpoints
75 );
76end FTU_top;
77
78architecture Behavioral of FTU_top is
79
80 signal reset_sig : STD_LOGIC; -- initialized in FTU_control
81 signal dac_clr_sig : STD_LOGIC := '1'; -- not used in hardware, initialize to 1 at power up
82
83 --single-ended trigger signals for rate counter
84 signal patch_A_sig : STD_LOGIC := '0';
85 signal patch_B_sig : STD_LOGIC := '0';
86 signal patch_C_sig : STD_LOGIC := '0';
87 signal patch_D_sig : STD_LOGIC := '0';
88 signal trigger_sig : STD_LOGIC := '0';
89
90 --DAC/SPI interface
91 signal config_start_sig : STD_LOGIC; -- initialized in FTU_control
92 signal config_started_sig : STD_LOGIC; -- initialized in spi_interface
93 signal config_ready_sig : STD_LOGIC; -- initialized in spi_interface
94 signal dac_array_sig : dac_array_type; -- initialized in FTU_control
95
96 signal enable_array_sig : enable_array_type; -- initialized in FTU_control
97
98 --rate counter signals
99 signal cntr_reset_sig : STD_LOGIC; -- initialized in FTU_control
100 signal rate_array_sig : rate_array_type; -- initialized by counters
101 signal prescaling_sig : STD_LOGIC_VECTOR(7 downto 0); -- initialized in FTU_control
102 signal overflow_array : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
103 signal new_rate_A_sig : STD_LOGIC; -- initialized by patch A counter
104 signal new_rate_B_sig : STD_LOGIC; -- initialized by patch B counter
105 signal new_rate_C_sig : STD_LOGIC; -- initialized by patch C counter
106 signal new_rate_D_sig : STD_LOGIC; -- initialized by patch D counter
107 signal new_rate_t_sig : STD_LOGIC; -- initialized by trigger counter
108 signal new_rates_sig : STD_LOGIC := '0';
109
110 signal clk_50M_sig : STD_LOGIC; -- generated by internal DCM
111 signal clk_ready_sig : STD_LOGIC := '0'; -- set high by FTU_clk_gen when DCMs have locked
112
113 --signals for RAM control, all initialized in FTU_control
114 signal ram_ena_sig : STD_LOGIC;
115 signal ram_enb_sig : STD_LOGIC;
116 signal ram_wea_sig : STD_LOGIC_VECTOR(0 downto 0);
117 signal ram_web_sig : STD_LOGIC_VECTOR(0 downto 0);
118 signal ram_ada_sig : STD_LOGIC_VECTOR(4 downto 0);
119 signal ram_adb_sig : STD_LOGIC_VECTOR(3 downto 0);
120 signal ram_dia_sig : STD_LOGIC_VECTOR(7 downto 0);
121 signal ram_dib_sig : STD_LOGIC_VECTOR(15 downto 0);
122 signal ram_doa_sig : STD_LOGIC_VECTOR(7 downto 0);
123 signal ram_dob_sig : STD_LOGIC_VECTOR(15 downto 0);
124
125 component FTU_clk_gen
126 port(
127 clk : IN STD_LOGIC;
128 rst : IN STD_LOGIC;
129 clk_50 : OUT STD_LOGIC;
130 ready : OUT STD_LOGIC
131 );
132 end component;
133
134 component FTU_rate_counter is
135 port(
136 clk : in std_logic;
137 cntr_reset : in std_logic;
138 trigger : in std_logic;
139 prescaling : in std_logic_vector(7 downto 0);
140 counts : out integer range 0 to 2**16 - 1;
141 overflow : out std_logic;
142 new_rate : out std_logic
143 );
144 end component;
145
146 component FTU_control
147 port(
148 clk_50MHz : IN std_logic;
149 clk_ready : IN std_logic;
150 config_started : IN std_logic;
151 config_ready : IN std_logic;
152 ram_doa : IN STD_LOGIC_VECTOR(7 downto 0);
153 ram_dob : IN STD_LOGIC_VECTOR(15 downto 0);
154 rate_array : IN rate_array_type;
155 overflow_array : in STD_LOGIC_VECTOR(7 downto 0);
156 new_rates : IN std_logic;
157 reset : OUT std_logic;
158 config_start : OUT std_logic;
159 ram_ena : OUT std_logic;
160 ram_enb : OUT std_logic;
161 ram_wea : OUT STD_LOGIC_VECTOR(0 downto 0);
162 ram_web : OUT STD_LOGIC_VECTOR(0 downto 0);
163 ram_ada : OUT STD_LOGIC_VECTOR(4 downto 0);
164 ram_adb : OUT STD_LOGIC_VECTOR(3 downto 0);
165 ram_dia : OUT STD_LOGIC_VECTOR(7 downto 0);
166 ram_dib : OUT STD_LOGIC_VECTOR(15 downto 0);
167 dac_array : OUT dac_array_type;
168 enable_array : OUT enable_array_type;
169 cntr_reset : OUT STD_LOGIC;
170 prescaling : OUT STD_LOGIC_VECTOR(7 downto 0)
171 );
172 end component;
173
174 component FTU_spi_interface
175 port(
176 clk_50MHz : IN std_logic;
177 config_start : IN std_logic;
178 dac_array : IN dac_array_type;
179 config_ready : OUT std_logic;
180 config_started : OUT std_logic;
181 dac_cs : OUT std_logic;
182 mosi : OUT std_logic;
183 sclk : OUT std_logic
184 );
185 end component;
186
187 component FTU_dual_port_ram
188 port(
189 clka : IN std_logic;
190 ena : IN std_logic;
191 wea : IN std_logic_VECTOR(0 downto 0);
192 addra : IN std_logic_VECTOR(4 downto 0);
193 dina : IN std_logic_VECTOR(7 downto 0);
194 douta : OUT std_logic_VECTOR(7 downto 0);
195 clkb : IN std_logic;
196 enb : IN std_logic;
197 web : IN std_logic_VECTOR(0 downto 0);
198 addrb : IN std_logic_VECTOR(3 downto 0);
199 dinb : IN std_logic_VECTOR(15 downto 0);
200 doutb : OUT std_logic_VECTOR(15 downto 0)
201 );
202 end component;
203
204 -- Synplicity black box declaration
205 attribute syn_black_box : boolean;
206 attribute syn_black_box of FTU_dual_port_ram: component is true;
207
208begin
209
210 clr <= dac_clr_sig;
211
212 enables_A <= enable_array_sig(0)(8 downto 0);
213 enables_B <= enable_array_sig(1)(8 downto 0);
214 enables_C <= enable_array_sig(2)(8 downto 0);
215 enables_D <= enable_array_sig(3)(8 downto 0);
216
217 new_rates_sig <= new_rate_A_sig and new_rate_B_sig and new_rate_C_sig and new_rate_D_sig and new_rate_t_sig;
218
219 --differential input buffer for patch A
220 IBUFDS_LVDS_33_A : IBUFDS_LVDS_33
221 port map(
222 O => patch_A_sig,
223 I => patch_A_p,
224 IB => patch_A_n
225 );
226
227 --differential input buffer for patch B
228 IBUFDS_LVDS_33_B : IBUFDS_LVDS_33
229 port map(
230 O => patch_B_sig,
231 I => patch_B_p,
232 IB => patch_B_n
233 );
234
235 --differential input buffer for patch C
236 IBUFDS_LVDS_33_C : IBUFDS_LVDS_33
237 port map(
238 O => patch_C_sig,
239 I => patch_C_p,
240 IB => patch_C_n
241 );
242
243 --differential input buffer for patch D
244 IBUFDS_LVDS_33_D : IBUFDS_LVDS_33
245 port map(
246 O => patch_D_sig,
247 I => patch_D_p,
248 IB => patch_D_n
249 );
250
251 --differential input buffer for trigger
252 IBUFDS_LVDS_33_t : IBUFDS_LVDS_33
253 port map(
254 O => trigger_sig,
255 I => trig_prim_p,
256 IB => trig_prim_n
257 );
258
259 Inst_FTU_clk_gen : FTU_clk_gen
260 port map(
261 clk => ext_clk,
262 rst => reset_sig,
263 clk_50 => clk_50M_sig,
264 ready => clk_ready_sig
265 );
266
267 Inst_FTU_rate_counter_A : FTU_rate_counter
268 port map(
269 clk => clk_50M_sig,
270 cntr_reset => cntr_reset_sig,
271 trigger => patch_A_sig,
272 prescaling => prescaling_sig,
273 counts => rate_array_sig(0),
274 overflow => overflow_array(0),
275 new_rate => new_rate_A_sig
276 );
277
278 Inst_FTU_rate_counter_B : FTU_rate_counter
279 port map(
280 clk => clk_50M_sig,
281 cntr_reset => cntr_reset_sig,
282 trigger => patch_B_sig,
283 prescaling => prescaling_sig,
284 counts => rate_array_sig(1),
285 overflow => overflow_array(1),
286 new_rate => new_rate_B_sig
287 );
288
289 Inst_FTU_rate_counter_C : FTU_rate_counter
290 port map(
291 clk => clk_50M_sig,
292 cntr_reset => cntr_reset_sig,
293 trigger => patch_C_sig,
294 prescaling => prescaling_sig,
295 counts => rate_array_sig(2),
296 overflow => overflow_array(2),
297 new_rate => new_rate_C_sig
298 );
299
300 Inst_FTU_rate_counter_D : FTU_rate_counter
301 port map(
302 clk => clk_50M_sig,
303 cntr_reset => cntr_reset_sig,
304 trigger => patch_D_sig,
305 prescaling => prescaling_sig,
306 counts => rate_array_sig(3),
307 overflow => overflow_array(3),
308 new_rate => new_rate_D_sig
309 );
310
311 Inst_FTU_rate_counter_t : FTU_rate_counter
312 port map(
313 clk => clk_50M_sig,
314 cntr_reset => cntr_reset_sig,
315 trigger => trigger_sig,
316 prescaling => prescaling_sig,
317 counts => rate_array_sig(4),
318 overflow => overflow_array(4),
319 new_rate => new_rate_t_sig
320 );
321
322 Inst_FTU_control : FTU_control
323 port map(
324 clk_50MHz => clk_50M_sig,
325 clk_ready => clk_ready_sig,
326 config_started => config_started_sig,
327 config_ready => config_ready_sig,
328 ram_doa => ram_doa_sig,
329 ram_dob => ram_dob_sig,
330 rate_array => rate_array_sig,
331 overflow_array => overflow_array,
332 new_rates => new_rates_sig,
333 reset => reset_sig,
334 config_start => config_start_sig,
335 ram_ena => ram_ena_sig,
336 ram_enb => ram_enb_sig,
337 ram_wea => ram_wea_sig,
338 ram_web => ram_web_sig,
339 ram_ada => ram_ada_sig,
340 ram_adb => ram_adb_sig,
341 ram_dia => ram_dia_sig,
342 ram_dib => ram_dib_sig,
343 dac_array => dac_array_sig,
344 enable_array => enable_array_sig,
345 cntr_reset => cntr_reset_sig,
346 prescaling => prescaling_sig
347 );
348
349 Inst_FTU_spi_interface : FTU_spi_interface
350 port map(
351 clk_50MHz => clk_50M_sig,
352 config_start => config_start_sig,
353 dac_array => dac_array_sig,
354 config_ready => config_ready_sig,
355 config_started => config_started_sig,
356 dac_cs => cs_ld,
357 mosi => mosi,
358 sclk => sck
359 );
360
361 Inst_FTU_dual_port_ram : FTU_dual_port_ram
362 port map(
363 clka => clk_50M_sig,
364 ena => ram_ena_sig,
365 wea => ram_wea_sig,
366 addra => ram_ada_sig,
367 dina => ram_dia_sig,
368 douta => ram_doa_sig,
369 clkb => clk_50M_sig,
370 enb => ram_enb_sig,
371 web => ram_web_sig,
372 addrb => ram_adb_sig,
373 dinb => ram_dib_sig,
374 doutb => ram_dob_sig
375 );
376
377end Behavioral;
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