source: firmware/FTU/FTU_top.vhd@ 9911

Last change on this file since 9911 was 9911, checked in by weitzel, 15 years ago
FTU rate counting modified; now synthesis works
File size: 12.9 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 11:59:40 01/19/2010
6-- Design Name:
7-- Module Name: FTU_top - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Top level entity of FACT FTU board
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Revision 0.02 - New design of FTU firmware, 12.07.2010, Q. Weitzel
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21
22library IEEE;
23use IEEE.STD_LOGIC_1164.ALL;
24use IEEE.STD_LOGIC_ARITH.ALL;
25use IEEE.STD_LOGIC_UNSIGNED.ALL;
26
27library ftu_definitions;
28USE ftu_definitions.ftu_array_types.all;
29
30---- Uncomment the following library declaration if instantiating
31---- any Xilinx primitives in this code.
32library UNISIM;
33use UNISIM.VComponents.all;
34
35entity FTU_top is
36 port(
37 -- global control
38 ext_clk : IN STD_LOGIC; -- external clock from FTU board
39 brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address
40 brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID
41
42 -- rate counters LVDS inputs
43 -- use IBUFDS differential input buffer
44 patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch
45 patch_A_n : IN STD_LOGIC;
46 patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch
47 patch_B_n : IN STD_LOGIC;
48 patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch
49 patch_C_n : IN STD_LOGIC;
50 patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch
51 patch_D_n : IN STD_LOGIC;
52 trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit
53 trig_prim_n : IN STD_LOGIC;
54
55 -- DAC interface
56 sck : OUT STD_LOGIC; -- serial clock to DAC
57 mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in
58 clr : OUT STD_LOGIC; -- clear signal to DAC
59 cs_ld : OUT STD_LOGIC; -- chip select or load to DAC
60
61 -- RS-485 interface to FTM
62 rx : IN STD_LOGIC; -- serial data from FTM
63 tx : OUT STD_LOGIC; -- serial data to FTM
64 rx_en : OUT STD_LOGIC; -- enable RS-485 receiver
65 tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter
66
67 -- analog buffer enable
68 enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
69 enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
70 enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
71 enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
72
73 -- testpoints
74 TP_A : OUT STD_LOGIC_VECTOR(11 downto 0) -- testpoints
75 );
76end FTU_top;
77
78architecture Behavioral of FTU_top is
79
80 signal reset_sig : STD_LOGIC; -- initialized in FTU_control
81 signal dac_clr_sig : STD_LOGIC := '1'; -- not used in hardware, initialize to 1 at power up
82
83 --single-ended trigger signals for rate counter
84 signal patch_A_sig : STD_LOGIC := '0';
85 signal patch_B_sig : STD_LOGIC := '0';
86 signal patch_C_sig : STD_LOGIC := '0';
87 signal patch_D_sig : STD_LOGIC := '0';
88 signal trigger_sig : STD_LOGIC := '0';
89
90 --DAC/SPI interface
91 signal config_start_sig : STD_LOGIC; -- initialized in FTU_control
92 signal config_started_sig : STD_LOGIC; -- initialized in spi_interface
93 signal config_ready_sig : STD_LOGIC; -- initialized in spi_interface
94 signal dac_array_sig : dac_array_type; -- initialized in FTU_control
95
96 signal enable_array_sig : enable_array_type; -- initialized in FTU_control
97
98 --rate counter signals
99 signal cntr_reset_sig : STD_LOGIC; -- initialized in FTU_control
100 signal rate_array_sig : rate_array_type; -- initialized by counters
101 signal prescaling_sig : STD_LOGIC_VECTOR(7 downto 0); -- initialized in FTU_control
102 signal overflow_array : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
103 signal new_rate_A_sig : STD_LOGIC; -- initialized by patch A counter
104 signal new_rate_B_sig : STD_LOGIC; -- initialized by patch B counter
105 signal new_rate_C_sig : STD_LOGIC; -- initialized by patch C counter
106 signal new_rate_D_sig : STD_LOGIC; -- initialized by patch D counter
107 signal new_rate_t_sig : STD_LOGIC; -- initialized by trigger counter
108 signal new_rates_sig : STD_LOGIC := '0';
109
110 signal clk_50M_sig : STD_LOGIC; -- generated by internal DCM
111 signal clk_ready_sig : STD_LOGIC := '0'; -- set high by FTU_clk_gen when DCMs have locked
112
113 --signals for RAM control, all initialized in FTU_control
114 signal ram_ena_sig : STD_LOGIC;
115 signal ram_enb_sig : STD_LOGIC;
116 signal ram_wea_sig : STD_LOGIC_VECTOR(0 downto 0);
117 signal ram_web_sig : STD_LOGIC_VECTOR(0 downto 0);
118 signal ram_ada_sig : STD_LOGIC_VECTOR(4 downto 0);
119 signal ram_adb_sig : STD_LOGIC_VECTOR(3 downto 0);
120 signal ram_dia_sig : STD_LOGIC_VECTOR(7 downto 0);
121 signal ram_dib_sig : STD_LOGIC_VECTOR(15 downto 0);
122 signal ram_doa_sig : STD_LOGIC_VECTOR(7 downto 0);
123 signal ram_dob_sig : STD_LOGIC_VECTOR(15 downto 0);
124
125 component FTU_clk_gen
126 port(
127 clk : IN STD_LOGIC;
128 rst : IN STD_LOGIC;
129 clk_50 : OUT STD_LOGIC;
130 ready : OUT STD_LOGIC
131 );
132 end component;
133
134 component FTU_rate_counter is
135 port(
136 clk : in std_logic;
137 cntr_reset : in std_logic;
138 trigger : in std_logic;
139 prescaling : in std_logic_vector(7 downto 0);
140 counts : out integer range 0 to 2**16 - 1;
141 overflow : out std_logic;
142 new_rate : out std_logic
143 );
144 end component;
145
146 component FTU_control
147 port(
148 clk_50MHz : IN std_logic;
149 clk_ready : IN std_logic;
150 config_started : IN std_logic;
151 config_ready : IN std_logic;
152 ram_doa : IN STD_LOGIC_VECTOR(7 downto 0);
153 ram_dob : IN STD_LOGIC_VECTOR(15 downto 0);
154 rate_array : IN rate_array_type;
155 overflow_array : in STD_LOGIC_VECTOR(7 downto 0);
156 new_rates : IN std_logic;
157 reset : OUT std_logic;
158 config_start : OUT std_logic;
159 ram_ena : OUT std_logic;
160 ram_enb : OUT std_logic;
161 ram_wea : OUT STD_LOGIC_VECTOR(0 downto 0);
162 ram_web : OUT STD_LOGIC_VECTOR(0 downto 0);
163 ram_ada : OUT STD_LOGIC_VECTOR(4 downto 0);
164 ram_adb : OUT STD_LOGIC_VECTOR(3 downto 0);
165 ram_dia : OUT STD_LOGIC_VECTOR(7 downto 0);
166 ram_dib : OUT STD_LOGIC_VECTOR(15 downto 0);
167 dac_array : OUT dac_array_type;
168 enable_array : OUT enable_array_type;
169 cntr_reset : OUT STD_LOGIC;
170 prescaling : OUT STD_LOGIC_VECTOR(7 downto 0)
171 );
172 end component;
173
174 component FTU_spi_interface
175 port(
176 clk_50MHz : IN std_logic;
177 config_start : IN std_logic;
178 dac_array : IN dac_array_type;
179 config_ready : OUT std_logic;
180 config_started : OUT std_logic;
181 dac_cs : OUT std_logic;
182 mosi : OUT std_logic;
183 sclk : OUT std_logic
184 );
185 end component;
186
187 component FTU_dual_port_ram
188 port(
189 clka : IN std_logic;
190 ena : IN std_logic;
191 wea : IN std_logic_VECTOR(0 downto 0);
192 addra : IN std_logic_VECTOR(4 downto 0);
193 dina : IN std_logic_VECTOR(7 downto 0);
194 douta : OUT std_logic_VECTOR(7 downto 0);
195 clkb : IN std_logic;
196 enb : IN std_logic;
197 web : IN std_logic_VECTOR(0 downto 0);
198 addrb : IN std_logic_VECTOR(3 downto 0);
199 dinb : IN std_logic_VECTOR(15 downto 0);
200 doutb : OUT std_logic_VECTOR(15 downto 0)
201 );
202 end component;
203
204 -- Synplicity black box declaration
205 attribute syn_black_box : boolean;
206 attribute syn_black_box of FTU_dual_port_ram: component is true;
207 -- avoid "black box" warning during synthesis
208 attribute box_type : string;
209 attribute box_type of FTU_dual_port_ram: component is "black_box";
210
211begin
212
213 clr <= dac_clr_sig;
214
215 enables_A <= enable_array_sig(0)(8 downto 0);
216 enables_B <= enable_array_sig(1)(8 downto 0);
217 enables_C <= enable_array_sig(2)(8 downto 0);
218 enables_D <= enable_array_sig(3)(8 downto 0);
219
220 new_rates_sig <= new_rate_A_sig and new_rate_B_sig and new_rate_C_sig and new_rate_D_sig and new_rate_t_sig;
221
222 --differential input buffer for patch A
223 IBUFDS_LVDS_33_A : IBUFDS_LVDS_33
224 port map(
225 O => patch_A_sig,
226 I => patch_A_p,
227 IB => patch_A_n
228 );
229
230 --differential input buffer for patch B
231 IBUFDS_LVDS_33_B : IBUFDS_LVDS_33
232 port map(
233 O => patch_B_sig,
234 I => patch_B_p,
235 IB => patch_B_n
236 );
237
238 --differential input buffer for patch C
239 IBUFDS_LVDS_33_C : IBUFDS_LVDS_33
240 port map(
241 O => patch_C_sig,
242 I => patch_C_p,
243 IB => patch_C_n
244 );
245
246 --differential input buffer for patch D
247 IBUFDS_LVDS_33_D : IBUFDS_LVDS_33
248 port map(
249 O => patch_D_sig,
250 I => patch_D_p,
251 IB => patch_D_n
252 );
253
254 --differential input buffer for trigger
255 IBUFDS_LVDS_33_t : IBUFDS_LVDS_33
256 port map(
257 O => trigger_sig,
258 I => trig_prim_p,
259 IB => trig_prim_n
260 );
261
262 Inst_FTU_clk_gen : FTU_clk_gen
263 port map(
264 clk => ext_clk,
265 rst => reset_sig,
266 clk_50 => clk_50M_sig,
267 ready => clk_ready_sig
268 );
269
270 Inst_FTU_rate_counter_A : FTU_rate_counter
271 port map(
272 clk => clk_50M_sig,
273 cntr_reset => cntr_reset_sig,
274 trigger => patch_A_sig,
275 prescaling => prescaling_sig,
276 counts => rate_array_sig(0),
277 overflow => overflow_array(0),
278 new_rate => new_rate_A_sig
279 );
280
281 Inst_FTU_rate_counter_B : FTU_rate_counter
282 port map(
283 clk => clk_50M_sig,
284 cntr_reset => cntr_reset_sig,
285 trigger => patch_B_sig,
286 prescaling => prescaling_sig,
287 counts => rate_array_sig(1),
288 overflow => overflow_array(1),
289 new_rate => new_rate_B_sig
290 );
291
292 Inst_FTU_rate_counter_C : FTU_rate_counter
293 port map(
294 clk => clk_50M_sig,
295 cntr_reset => cntr_reset_sig,
296 trigger => patch_C_sig,
297 prescaling => prescaling_sig,
298 counts => rate_array_sig(2),
299 overflow => overflow_array(2),
300 new_rate => new_rate_C_sig
301 );
302
303 Inst_FTU_rate_counter_D : FTU_rate_counter
304 port map(
305 clk => clk_50M_sig,
306 cntr_reset => cntr_reset_sig,
307 trigger => patch_D_sig,
308 prescaling => prescaling_sig,
309 counts => rate_array_sig(3),
310 overflow => overflow_array(3),
311 new_rate => new_rate_D_sig
312 );
313
314 Inst_FTU_rate_counter_t : FTU_rate_counter
315 port map(
316 clk => clk_50M_sig,
317 cntr_reset => cntr_reset_sig,
318 trigger => trigger_sig,
319 prescaling => prescaling_sig,
320 counts => rate_array_sig(4),
321 overflow => overflow_array(4),
322 new_rate => new_rate_t_sig
323 );
324
325 Inst_FTU_control : FTU_control
326 port map(
327 clk_50MHz => clk_50M_sig,
328 clk_ready => clk_ready_sig,
329 config_started => config_started_sig,
330 config_ready => config_ready_sig,
331 ram_doa => ram_doa_sig,
332 ram_dob => ram_dob_sig,
333 rate_array => rate_array_sig,
334 overflow_array => overflow_array,
335 new_rates => new_rates_sig,
336 reset => reset_sig,
337 config_start => config_start_sig,
338 ram_ena => ram_ena_sig,
339 ram_enb => ram_enb_sig,
340 ram_wea => ram_wea_sig,
341 ram_web => ram_web_sig,
342 ram_ada => ram_ada_sig,
343 ram_adb => ram_adb_sig,
344 ram_dia => ram_dia_sig,
345 ram_dib => ram_dib_sig,
346 dac_array => dac_array_sig,
347 enable_array => enable_array_sig,
348 cntr_reset => cntr_reset_sig,
349 prescaling => prescaling_sig
350 );
351
352 Inst_FTU_spi_interface : FTU_spi_interface
353 port map(
354 clk_50MHz => clk_50M_sig,
355 config_start => config_start_sig,
356 dac_array => dac_array_sig,
357 config_ready => config_ready_sig,
358 config_started => config_started_sig,
359 dac_cs => cs_ld,
360 mosi => mosi,
361 sclk => sck
362 );
363
364 Inst_FTU_dual_port_ram : FTU_dual_port_ram
365 port map(
366 clka => clk_50M_sig,
367 ena => ram_ena_sig,
368 wea => ram_wea_sig,
369 addra => ram_ada_sig,
370 dina => ram_dia_sig,
371 douta => ram_doa_sig,
372 clkb => clk_50M_sig,
373 enb => ram_enb_sig,
374 web => ram_web_sig,
375 addrb => ram_adb_sig,
376 dinb => ram_dib_sig,
377 doutb => ram_dob_sig
378 );
379
380end Behavioral;
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