source: firmware/FTU/FTU_top.vhd@ 9928

Last change on this file since 9928 was 9928, checked in by weitzel, 16 years ago
first version of RS485 interface added to FTU firmware; not yet connected to main control state machine
File size: 15.4 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 11:59:40 01/19/2010
6-- Design Name:
7-- Module Name: FTU_top - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Top level entity of FACT FTU board
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Revision 0.02 - New design of FTU firmware, 12.07.2010, Q. Weitzel
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21
22library IEEE;
23use IEEE.STD_LOGIC_1164.ALL;
24use IEEE.STD_LOGIC_ARITH.ALL;
25use IEEE.STD_LOGIC_UNSIGNED.ALL;
26
27library ftu_definitions;
28USE ftu_definitions.ftu_array_types.all;
29USE ftu_definitions.ftu_constants.all;
30
31---- Uncomment the following library declaration if instantiating
32---- any Xilinx primitives in this code.
33library UNISIM;
34use UNISIM.VComponents.all;
35
36entity FTU_top is
37 port(
38 -- global control
39 ext_clk : IN STD_LOGIC; -- external clock from FTU board
40 brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address
41 brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID
42
43 -- rate counters LVDS inputs
44 -- use IBUFDS differential input buffer
45 patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch
46 patch_A_n : IN STD_LOGIC;
47 patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch
48 patch_B_n : IN STD_LOGIC;
49 patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch
50 patch_C_n : IN STD_LOGIC;
51 patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch
52 patch_D_n : IN STD_LOGIC;
53 trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit
54 trig_prim_n : IN STD_LOGIC;
55
56 -- DAC interface
57 sck : OUT STD_LOGIC; -- serial clock to DAC
58 mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in
59 clr : OUT STD_LOGIC; -- clear signal to DAC
60 cs_ld : OUT STD_LOGIC; -- chip select or load to DAC
61
62 -- RS-485 interface to FTM
63 rx : IN STD_LOGIC; -- serial data from FTM
64 tx : OUT STD_LOGIC; -- serial data to FTM
65 rx_en : OUT STD_LOGIC; -- enable RS-485 receiver
66 tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter
67
68 -- analog buffer enable
69 enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
70 enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
71 enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
72 enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
73
74 -- testpoints
75 TP_A : OUT STD_LOGIC_VECTOR(11 downto 0) -- testpoints
76 );
77end FTU_top;
78
79architecture Behavioral of FTU_top is
80
81 signal reset_sig : STD_LOGIC; -- initialized in FTU_control
82 signal dac_clr_sig : STD_LOGIC := '1'; -- not used in hardware, initialize to 1 at power up
83
84 --single-ended trigger signals for rate counter
85 signal patch_A_sig : STD_LOGIC := '0';
86 signal patch_B_sig : STD_LOGIC := '0';
87 signal patch_C_sig : STD_LOGIC := '0';
88 signal patch_D_sig : STD_LOGIC := '0';
89 signal trigger_sig : STD_LOGIC := '0';
90
91 --DAC/SPI interface
92 signal config_start_sig : STD_LOGIC; -- initialized in FTU_control
93 signal config_started_sig : STD_LOGIC; -- initialized in spi_interface
94 signal config_ready_sig : STD_LOGIC; -- initialized in spi_interface
95 signal dac_array_sig : dac_array_type; -- initialized in FTU_control
96
97 signal enable_array_sig : enable_array_type; -- initialized in FTU_control
98
99 --rate counter signals
100 signal cntr_reset_sig : STD_LOGIC; -- initialized in FTU_control
101 signal rate_array_sig : rate_array_type; -- initialized by counters
102 signal prescaling_sig : STD_LOGIC_VECTOR(7 downto 0); -- initialized in FTU_control
103 signal overflow_array : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
104 signal new_rate_A_sig : STD_LOGIC; -- initialized by patch A counter
105 signal new_rate_B_sig : STD_LOGIC; -- initialized by patch B counter
106 signal new_rate_C_sig : STD_LOGIC; -- initialized by patch C counter
107 signal new_rate_D_sig : STD_LOGIC; -- initialized by patch D counter
108 signal new_rate_t_sig : STD_LOGIC; -- initialized by trigger counter
109 signal new_rates_sig : STD_LOGIC := '0';
110
111 signal clk_50M_sig : STD_LOGIC; -- generated by internal DCM
112 signal clk_ready_sig : STD_LOGIC := '0'; -- set high by FTU_clk_gen when DCMs have locked
113
114 --signals for RAM control, all initialized in FTU_control
115 signal ram_ena_sig : STD_LOGIC;
116 signal ram_enb_sig : STD_LOGIC;
117 signal ram_wea_sig : STD_LOGIC_VECTOR(0 downto 0);
118 signal ram_web_sig : STD_LOGIC_VECTOR(0 downto 0);
119 signal ram_ada_sig : STD_LOGIC_VECTOR(4 downto 0);
120 signal ram_adb_sig : STD_LOGIC_VECTOR(3 downto 0);
121 signal ram_dia_sig : STD_LOGIC_VECTOR(7 downto 0);
122 signal ram_dib_sig : STD_LOGIC_VECTOR(15 downto 0);
123 signal ram_doa_sig : STD_LOGIC_VECTOR(7 downto 0);
124 signal ram_dob_sig : STD_LOGIC_VECTOR(15 downto 0);
125
126 component FTU_clk_gen
127 port(
128 clk : IN STD_LOGIC;
129 rst : IN STD_LOGIC;
130 clk_50 : OUT STD_LOGIC;
131 ready : OUT STD_LOGIC
132 );
133 end component;
134
135 component FTU_rate_counter is
136 port(
137 clk : in std_logic;
138 cntr_reset : in std_logic;
139 trigger : in std_logic;
140 prescaling : in std_logic_vector(7 downto 0);
141 counts : out integer range 0 to 2**16 - 1;
142 overflow : out std_logic;
143 new_rate : out std_logic
144 );
145 end component;
146
147 component FTU_control
148 port(
149 clk_50MHz : IN std_logic;
150 clk_ready : IN std_logic;
151 config_started : IN std_logic;
152 config_ready : IN std_logic;
153 ram_doa : IN STD_LOGIC_VECTOR(7 downto 0);
154 ram_dob : IN STD_LOGIC_VECTOR(15 downto 0);
155 rate_array : IN rate_array_type;
156 overflow_array : in STD_LOGIC_VECTOR(7 downto 0);
157 new_rates : IN std_logic;
158 reset : OUT std_logic;
159 config_start : OUT std_logic;
160 ram_ena : OUT std_logic;
161 ram_enb : OUT std_logic;
162 ram_wea : OUT STD_LOGIC_VECTOR(0 downto 0);
163 ram_web : OUT STD_LOGIC_VECTOR(0 downto 0);
164 ram_ada : OUT STD_LOGIC_VECTOR(4 downto 0);
165 ram_adb : OUT STD_LOGIC_VECTOR(3 downto 0);
166 ram_dia : OUT STD_LOGIC_VECTOR(7 downto 0);
167 ram_dib : OUT STD_LOGIC_VECTOR(15 downto 0);
168 dac_array : OUT dac_array_type;
169 enable_array : OUT enable_array_type;
170 cntr_reset : OUT STD_LOGIC;
171 prescaling : OUT STD_LOGIC_VECTOR(7 downto 0)
172 );
173 end component;
174
175 component FTU_spi_interface
176 port(
177 clk_50MHz : IN std_logic;
178 config_start : IN std_logic;
179 dac_array : IN dac_array_type;
180 config_ready : OUT std_logic;
181 config_started : OUT std_logic;
182 dac_cs : OUT std_logic;
183 mosi : OUT std_logic;
184 sclk : OUT std_logic
185 );
186 end component;
187
188 component FTU_rs485_control
189 port(
190 main_clk : IN std_logic;
191 brd_add : IN std_logic_vector(5 downto 0);
192 rx_d : IN std_logic;
193 rates_ready : IN std_logic;
194 DACs_ready : IN std_logic;
195 enables_ready : IN std_logic;
196 prescaling_ready : IN std_logic;
197 rate_array_rs485 : IN rate_array_type;
198 overflow_array_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0);
199 dac_array_rs485_in : IN dac_array_type;
200 enable_array_rs485_in : IN enable_array_type;
201 prescaling_rs485_in : IN STD_LOGIC_VECTOR(7 downto 0);
202 rx_en : OUT std_logic;
203 tx_d : OUT std_logic;
204 tx_en : OUT std_logic;
205 new_DACs : OUT std_logic;
206 new_enables : OUT std_logic;
207 new_prescaling : OUT std_logic;
208 read_rates : OUT std_logic;
209 read_DACs : OUT std_logic;
210 read_enables : OUT std_logic;
211 read_prescaling : OUT std_logic;
212 --rs485_error : OUT std_logic; -- to be discussed!
213 dac_array_rs485_out : OUT dac_array_type;
214 enable_array_rs485_out : OUT enable_array_type;
215 prescaling_rs485_out : OUT STD_LOGIC_VECTOR(7 downto 0)
216 );
217 end component;
218
219 component FTU_dual_port_ram
220 port(
221 clka : IN std_logic;
222 ena : IN std_logic;
223 wea : IN std_logic_VECTOR(0 downto 0);
224 addra : IN std_logic_VECTOR(4 downto 0);
225 dina : IN std_logic_VECTOR(7 downto 0);
226 douta : OUT std_logic_VECTOR(7 downto 0);
227 clkb : IN std_logic;
228 enb : IN std_logic;
229 web : IN std_logic_VECTOR(0 downto 0);
230 addrb : IN std_logic_VECTOR(3 downto 0);
231 dinb : IN std_logic_VECTOR(15 downto 0);
232 doutb : OUT std_logic_VECTOR(15 downto 0)
233 );
234 end component;
235
236 -- Synplicity black box declaration
237 attribute syn_black_box : boolean;
238 attribute syn_black_box of FTU_dual_port_ram: component is true;
239 -- avoid "black box" warning during synthesis
240 attribute box_type : string;
241 attribute box_type of FTU_dual_port_ram: component is "black_box";
242
243begin
244
245 clr <= dac_clr_sig;
246
247 enables_A <= enable_array_sig(0)(8 downto 0);
248 enables_B <= enable_array_sig(1)(8 downto 0);
249 enables_C <= enable_array_sig(2)(8 downto 0);
250 enables_D <= enable_array_sig(3)(8 downto 0);
251
252 new_rates_sig <= new_rate_A_sig and new_rate_B_sig and new_rate_C_sig and new_rate_D_sig and new_rate_t_sig;
253
254 --differential input buffer for patch A
255 IBUFDS_LVDS_33_A : IBUFDS_LVDS_33
256 port map(
257 O => patch_A_sig,
258 I => patch_A_p,
259 IB => patch_A_n
260 );
261
262 --differential input buffer for patch B
263 IBUFDS_LVDS_33_B : IBUFDS_LVDS_33
264 port map(
265 O => patch_B_sig,
266 I => patch_B_p,
267 IB => patch_B_n
268 );
269
270 --differential input buffer for patch C
271 IBUFDS_LVDS_33_C : IBUFDS_LVDS_33
272 port map(
273 O => patch_C_sig,
274 I => patch_C_p,
275 IB => patch_C_n
276 );
277
278 --differential input buffer for patch D
279 IBUFDS_LVDS_33_D : IBUFDS_LVDS_33
280 port map(
281 O => patch_D_sig,
282 I => patch_D_p,
283 IB => patch_D_n
284 );
285
286 --differential input buffer for trigger
287 IBUFDS_LVDS_33_t : IBUFDS_LVDS_33
288 port map(
289 O => trigger_sig,
290 I => trig_prim_p,
291 IB => trig_prim_n
292 );
293
294 Inst_FTU_clk_gen : FTU_clk_gen
295 port map(
296 clk => ext_clk,
297 rst => reset_sig,
298 clk_50 => clk_50M_sig,
299 ready => clk_ready_sig
300 );
301
302 Inst_FTU_rate_counter_A : FTU_rate_counter
303 port map(
304 clk => clk_50M_sig,
305 cntr_reset => cntr_reset_sig,
306 trigger => patch_A_sig,
307 prescaling => prescaling_sig,
308 counts => rate_array_sig(0),
309 overflow => overflow_array(0),
310 new_rate => new_rate_A_sig
311 );
312
313 Inst_FTU_rate_counter_B : FTU_rate_counter
314 port map(
315 clk => clk_50M_sig,
316 cntr_reset => cntr_reset_sig,
317 trigger => patch_B_sig,
318 prescaling => prescaling_sig,
319 counts => rate_array_sig(1),
320 overflow => overflow_array(1),
321 new_rate => new_rate_B_sig
322 );
323
324 Inst_FTU_rate_counter_C : FTU_rate_counter
325 port map(
326 clk => clk_50M_sig,
327 cntr_reset => cntr_reset_sig,
328 trigger => patch_C_sig,
329 prescaling => prescaling_sig,
330 counts => rate_array_sig(2),
331 overflow => overflow_array(2),
332 new_rate => new_rate_C_sig
333 );
334
335 Inst_FTU_rate_counter_D : FTU_rate_counter
336 port map(
337 clk => clk_50M_sig,
338 cntr_reset => cntr_reset_sig,
339 trigger => patch_D_sig,
340 prescaling => prescaling_sig,
341 counts => rate_array_sig(3),
342 overflow => overflow_array(3),
343 new_rate => new_rate_D_sig
344 );
345
346 Inst_FTU_rate_counter_t : FTU_rate_counter
347 port map(
348 clk => clk_50M_sig,
349 cntr_reset => cntr_reset_sig,
350 trigger => trigger_sig,
351 prescaling => prescaling_sig,
352 counts => rate_array_sig(4),
353 overflow => overflow_array(4),
354 new_rate => new_rate_t_sig
355 );
356
357 Inst_FTU_control : FTU_control
358 port map(
359 clk_50MHz => clk_50M_sig,
360 clk_ready => clk_ready_sig,
361 config_started => config_started_sig,
362 config_ready => config_ready_sig,
363 ram_doa => ram_doa_sig,
364 ram_dob => ram_dob_sig,
365 rate_array => rate_array_sig,
366 overflow_array => overflow_array,
367 new_rates => new_rates_sig,
368 reset => reset_sig,
369 config_start => config_start_sig,
370 ram_ena => ram_ena_sig,
371 ram_enb => ram_enb_sig,
372 ram_wea => ram_wea_sig,
373 ram_web => ram_web_sig,
374 ram_ada => ram_ada_sig,
375 ram_adb => ram_adb_sig,
376 ram_dia => ram_dia_sig,
377 ram_dib => ram_dib_sig,
378 dac_array => dac_array_sig,
379 enable_array => enable_array_sig,
380 cntr_reset => cntr_reset_sig,
381 prescaling => prescaling_sig
382 );
383
384 Inst_FTU_spi_interface : FTU_spi_interface
385 port map(
386 clk_50MHz => clk_50M_sig,
387 config_start => config_start_sig,
388 dac_array => dac_array_sig,
389 config_ready => config_ready_sig,
390 config_started => config_started_sig,
391 dac_cs => cs_ld,
392 mosi => mosi,
393 sclk => sck
394 );
395
396 Inst_FTU_rs485_control : FTU_rs485_control
397 port map(
398 main_clk => clk_50M_sig,
399 brd_add => brd_add,
400 rx_d => rx,
401 rates_ready => '0',
402 DACs_ready => '0',
403 enables_ready => '0',
404 prescaling_ready => '0',
405 rate_array_rs485 => (0,0,0,0,0),
406 overflow_array_rs485_in => "00000000",
407 dac_array_rs485_in => DEFAULT_DAC,
408 enable_array_rs485_in => DEFAULT_ENABLE,
409 prescaling_rs485_in => conv_std_logic_vector(DEFAULT_PRESCALING,8),
410 rx_en => rx_en,
411 tx_d => tx,
412 tx_en => tx_en,
413 new_DACs => open,
414 new_enables => open,
415 new_prescaling => open,
416 read_rates => open,
417 read_DACs => open,
418 read_enables => open,
419 read_prescaling => open,
420 --rs485_error =>, -- to be discussed!
421 dac_array_rs485_out => open,
422 enable_array_rs485_out => open,
423 prescaling_rs485_out => open
424 );
425
426 Inst_FTU_dual_port_ram : FTU_dual_port_ram
427 port map(
428 clka => clk_50M_sig,
429 ena => ram_ena_sig,
430 wea => ram_wea_sig,
431 addra => ram_ada_sig,
432 dina => ram_dia_sig,
433 douta => ram_doa_sig,
434 clkb => clk_50M_sig,
435 enb => ram_enb_sig,
436 web => ram_web_sig,
437 addrb => ram_adb_sig,
438 dinb => ram_dib_sig,
439 doutb => ram_dob_sig
440 );
441
442end Behavioral;
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