source: firmware/FTU/FTU_top_tb.vhd@ 10047

Last change on this file since 10047 was 10037, checked in by weitzel, 14 years ago
FTU counter changed from 16 to 30 bit
File size: 13.0 KB
Line 
1--------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 12.07.2010
6-- Design Name:
7-- Module Name: FTU_top_tb.vhd
8-- Project Name:
9-- Target Device:
10-- Tool versions:
11-- Description: Testbench for top level entity of FACT FTU board
12--
13-- VHDL Test Bench Created by ISE for module: FTU_top
14--
15-- Dependencies:
16--
17-- Revision:
18-- Revision 0.01 - File Created
19-- Additional Comments:
20--
21-- Notes:
22-- This testbench has been automatically generated using types std_logic and
23-- std_logic_vector for the ports of the unit under test. Xilinx recommends
24-- that these types always be used for the top-level I/O of a design in order
25-- to guarantee that the testbench will bind correctly to the post-implementation
26-- simulation model.
27--------------------------------------------------------------------------------
28library IEEE;
29use IEEE.STD_LOGIC_1164.ALL;
30use IEEE.STD_LOGIC_UNSIGNED.ALL;
31use IEEE.NUMERIC_STD.ALL;
32
33library UNISIM;
34use UNISIM.VComponents.all;
35
36entity FTU_top_tb is
37end FTU_top_tb;
38
39architecture behavior of FTU_top_tb is
40
41 -- Component Declaration for the Unit Under Test (UUT)
42
43 component FTU_top
44 port(
45 -- global control
46 ext_clk : IN STD_LOGIC; -- external clock from FTU board
47 brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address
48 --brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID
49
50 -- rate counters LVDS inputs
51 -- use IBUFDS differential input buffer
52 patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch
53 patch_A_n : IN STD_LOGIC;
54 patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch
55 patch_B_n : IN STD_LOGIC;
56 patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch
57 patch_C_n : IN STD_LOGIC;
58 patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch
59 patch_D_n : IN STD_LOGIC;
60 trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit
61 trig_prim_n : IN STD_LOGIC;
62
63 -- DAC interface
64 sck : OUT STD_LOGIC; -- serial clock to DAC
65 mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in
66 clr : OUT STD_LOGIC; -- clear signal to DAC
67 cs_ld : OUT STD_LOGIC; -- chip select or load to DAC
68
69 -- RS-485 interface to FTM
70 rx : IN STD_LOGIC; -- serial data from FTM
71 tx : OUT STD_LOGIC; -- serial data to FTM
72 rx_en : OUT STD_LOGIC; -- enable RS-485 receiver
73 tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter
74
75 -- analog buffer enable
76 enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
77 enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
78 enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
79 enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
80
81 -- testpoints
82 TP_A : OUT STD_LOGIC_VECTOR(11 downto 0) -- testpoints
83 );
84 end component;
85
86 --Inputs
87 signal ext_clk : STD_LOGIC := '0';
88 signal brd_add : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
89 --signal brd_id : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
90 signal patch_A_p : STD_LOGIC := '0';
91 signal patch_A_n : STD_LOGIC := '0';
92 signal patch_B_p : STD_LOGIC := '0';
93 signal patch_B_n : STD_LOGIC := '0';
94 signal patch_C_p : STD_LOGIC := '0';
95 signal patch_C_n : STD_LOGIC := '0';
96 signal patch_D_p : STD_LOGIC := '0';
97 signal patch_D_n : STD_LOGIC := '0';
98 signal trig_prim_p : STD_LOGIC := '0';
99 signal trig_prim_n : STD_LOGIC := '0';
100 signal rx : STD_LOGIC := '1';
101
102 --Outputs
103 signal enables_A : STD_LOGIC_VECTOR(8 downto 0);
104 signal enables_B : STD_LOGIC_VECTOR(8 downto 0);
105 signal enables_C : STD_LOGIC_VECTOR(8 downto 0);
106 signal enables_D : STD_LOGIC_VECTOR(8 downto 0);
107 signal clr : STD_LOGIC;
108 signal cs_ld : STD_LOGIC;
109 signal sck : STD_LOGIC;
110 signal mosi : STD_LOGIC;
111 signal tx : STD_LOGIC;
112 signal rx_en : STD_LOGIC;
113 signal tx_en : STD_LOGIC;
114 signal TP_A : STD_LOGIC_VECTOR(11 downto 0);
115
116 --single-ended trigger signals
117 signal patch_A_sig : STD_LOGIC := '0';
118 signal patch_B_sig : STD_LOGIC := '0';
119 signal patch_C_sig : STD_LOGIC := '0';
120 signal patch_D_sig : STD_LOGIC := '0';
121 signal trigger_sig : STD_LOGIC := '0';
122
123 -- Clock period definitions
124 constant ext_clk_period : TIME := 20 ns;
125 constant baud_rate_period : TIME := 4 us;
126
127begin
128
129 -- Instantiate the Unit Under Test (UUT)
130 uut: FTU_top
131 port map(
132 ext_clk => ext_clk,
133 brd_add => brd_add,
134 --brd_id => brd_id,
135 patch_A_p => patch_A_p,
136 patch_A_n => patch_A_n,
137 patch_B_p => patch_B_p,
138 patch_B_n => patch_B_n,
139 patch_C_p => patch_C_p,
140 patch_C_n => patch_C_n,
141 patch_D_p => patch_D_p,
142 patch_D_n => patch_D_n,
143 trig_prim_p => trig_prim_p,
144 trig_prim_n => trig_prim_n,
145 rx => rx,
146 rx_en => rx_en,
147 enables_A => enables_A,
148 enables_B => enables_B,
149 enables_C => enables_C,
150 enables_D => enables_D,
151 clr => clr,
152 cs_ld => cs_ld,
153 sck => sck,
154 mosi => mosi,
155 tx => tx,
156 tx_en => tx_en,
157 TP_A => TP_A
158 );
159
160 --differential output buffer for patch A
161 OBUFDS_LVDS_33_A : OBUFDS_LVDS_33
162 port map(
163 O => patch_A_p,
164 OB => patch_A_n,
165 I => patch_A_sig
166 );
167
168 OBUFDS_LVDS_33_B : OBUFDS_LVDS_33
169 port map(
170 O => patch_B_p,
171 OB => patch_B_n,
172 I => patch_B_sig
173 );
174
175 OBUFDS_LVDS_33_C : OBUFDS_LVDS_33
176 port map(
177 O => patch_C_p,
178 OB => patch_C_n,
179 I => patch_C_sig
180 );
181
182 OBUFDS_LVDS_33_D : OBUFDS_LVDS_33
183 port map(
184 O => patch_D_p,
185 OB => patch_D_n,
186 I => patch_D_sig
187 );
188
189 OBUFDS_LVDS_33_t : OBUFDS_LVDS_33
190 port map(
191 O => trig_prim_p,
192 OB => trig_prim_n,
193 I => trigger_sig
194 );
195
196 -- Stimulus process for clock
197 ext_clk_proc: process
198 begin
199 ext_clk <= '0';
200 wait for ext_clk_period/2;
201 ext_clk <= '1';
202 wait for ext_clk_period/2;
203 end process ext_clk_proc;
204
205 -- Stimulus process for trigger
206 trigger_proc: process
207 begin
208 ---------------------------------------------------------------------------
209 -- FTU not yet initialized
210 ---------------------------------------------------------------------------
211 wait for 10us;
212 trigger_sig <= '1';
213 wait for 5ns;
214 trigger_sig <= '0';
215 wait for 99us;
216 trigger_sig <= '1';
217 wait for 5ns;
218 trigger_sig <= '0';
219 wait for 1us;
220 trigger_sig <= '1';
221 wait for 5ns;
222 trigger_sig <= '0';
223 ---------------------------------------------------------------------------
224 -- now FTU is initialized
225 ---------------------------------------------------------------------------
226 wait for 4us;
227 trigger_sig <= '1';
228 wait for 5ns;
229 trigger_sig <= '0';
230 wait for 4us;
231 trigger_sig <= '1';
232 wait for 5ns;
233 trigger_sig <= '0';
234 wait for 22us;
235 trigger_sig <= '1';
236 wait for 5ns;
237 trigger_sig <= '0';
238 wait for 1430us;
239 trigger_sig <= '1';
240 wait for 5ns;
241 trigger_sig <= '0';
242 wait for 400us;
243 trigger_sig <= '1';
244 wait for 5ns;
245 trigger_sig <= '0';
246 wait;
247 end process trigger_proc;
248
249 -- Stimulus process for RS485
250 rs485_proc: process
251
252 procedure assign_rs485 (data: std_logic_vector(7 downto 0)) is
253 begin
254 rx <= '0'; --start bit
255 wait for baud_rate_period;
256 rx <= data(0); --bit 0
257 wait for baud_rate_period;
258 rx <= data(1); --bit 1
259 wait for baud_rate_period;
260 rx <= data(2); --bit 2
261 wait for baud_rate_period;
262 rx <= data(3); --bit 3
263 wait for baud_rate_period;
264 rx <= data(4); --bit 4
265 wait for baud_rate_period;
266 rx <= data(5); --bit 5
267 wait for baud_rate_period;
268 rx <= data(6); --bit 6
269 wait for baud_rate_period;
270 rx <= data(7); --bit 7
271 wait for baud_rate_period;
272 rx <= '1'; --stop bit
273 wait for baud_rate_period;
274 rx <= '1'; --stop bit
275 wait for baud_rate_period;
276 end assign_rs485;
277
278 begin
279 ---------------------------------------------------------------------------
280 -- wait until FTU is initialized
281 ---------------------------------------------------------------------------
282 wait for 150us;
283 ---------------------------------------------------------------------------
284 -- test one RS485 command (28 byte)
285 ---------------------------------------------------------------------------
286 assign_rs485("01000000"); --start delimiter
287 wait for 0us;
288 assign_rs485("00000000"); --FTU address
289 wait for 0ns;
290 assign_rs485("11000000"); --FTM address
291 wait for 0ns;
292 assign_rs485("00000001"); --FTM firmware ID
293 wait for 0ns;
294 assign_rs485("00000010"); --instruction
295 wait for 0us;
296 assign_rs485("00000001"); --data byte 01
297 wait for 0ns;
298 assign_rs485("00000000"); --data byte 02
299 wait for 0ns;
300 assign_rs485("00000010"); --data byte 03
301 wait for 0ns;
302 assign_rs485("00000000"); --data byte 04
303 wait for 0ns;
304 assign_rs485("00000100"); --data byte 05
305 wait for 0ns;
306 assign_rs485("00000000"); --data byte 06
307 wait for 0ns;
308 assign_rs485("00001000"); --data byte 07
309 wait for 0ns;
310 assign_rs485("00000000"); --data byte 08
311 wait for 0ns;
312 assign_rs485("00010000"); --data byte 09
313 wait for 0ns;
314 assign_rs485("00000000"); --data byte 10
315 wait for 0ns;
316 assign_rs485("00000000"); --data byte 11
317 wait for 0ns;
318 assign_rs485("00000000"); --data byte 12
319 wait for 0ns;
320 assign_rs485("00000001"); --data byte 13
321 wait for 0ns;
322 assign_rs485("00000000"); --data byte 14
323 wait for 0ns;
324 assign_rs485("00000010"); --data byte 15
325 wait for 0ns;
326 assign_rs485("00000000"); --data byte 16
327 wait for 0ns;
328 assign_rs485("00000100"); --data byte 17
329 wait for 0ns;
330 assign_rs485("00000000"); --data byte 18
331 wait for 0ns;
332 assign_rs485("00001000"); --data byte 19
333 wait for 0ns;
334 assign_rs485("00000000"); --data byte 20
335 wait for 0ns;
336 assign_rs485("00010000"); --data byte 21
337 wait for 0ns;
338 assign_rs485("00000000"); --CRC error counter (not used)
339 wait for 0ns;
340 assign_rs485("00000000"); --check sum
341 ---------------------------------------------------------------------------
342 -- wait enough time and send another command
343 ---------------------------------------------------------------------------
344 wait for 1500us;
345 assign_rs485("01000000"); --start delimiter
346 wait for 0us;
347 assign_rs485("00000000"); --FTU address
348 wait for 0ns;
349 assign_rs485("11000000"); --FTM address
350 wait for 0ns;
351 assign_rs485("00000001"); --FTM firmware ID
352 wait for 0ns;
353 assign_rs485("00000101"); --instruction
354 wait for 0us;
355 assign_rs485("00000001"); --data byte 01
356 wait for 0ns;
357 assign_rs485("00000000"); --data byte 02
358 wait for 0ns;
359 assign_rs485("00000010"); --data byte 03
360 wait for 0ns;
361 assign_rs485("00000000"); --data byte 04
362 wait for 0ns;
363 assign_rs485("00000100"); --data byte 05
364 wait for 0ns;
365 assign_rs485("00000000"); --data byte 06
366 wait for 0ns;
367 assign_rs485("00001000"); --data byte 07
368 wait for 0ns;
369 assign_rs485("00000000"); --data byte 08
370 wait for 0ns;
371 assign_rs485("00010000"); --data byte 09
372 wait for 0ns;
373 assign_rs485("00000000"); --data byte 10
374 wait for 0ns;
375 assign_rs485("00000000"); --data byte 11
376 wait for 0ns;
377 assign_rs485("00000000"); --data byte 12
378 wait for 0ns;
379 assign_rs485("00000001"); --data byte 13
380 wait for 0ns;
381 assign_rs485("00000000"); --data byte 14
382 wait for 0ns;
383 assign_rs485("00000010"); --data byte 15
384 wait for 0ns;
385 assign_rs485("00000000"); --data byte 16
386 wait for 0ns;
387 assign_rs485("00000100"); --data byte 17
388 wait for 0ns;
389 assign_rs485("00000000"); --data byte 18
390 wait for 0ns;
391 assign_rs485("00001000"); --data byte 19
392 wait for 0ns;
393 assign_rs485("00000000"); --data byte 20
394 wait for 0ns;
395 assign_rs485("00010000"); --data byte 21
396 wait for 0ns;
397 assign_rs485("00000000"); --CRC error counter (not used)
398 wait for 0ns;
399 assign_rs485("00000000"); --check sum
400 ---------------------------------------------------------------------------
401 -- don't forget final wait!
402 ---------------------------------------------------------------------------
403 wait;
404
405 end process rs485_proc;
406
407end;
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