source: firmware/FTU/FTU_top_tb.vhd@ 9914

Last change on this file since 9914 was 9890, checked in by weitzel, 14 years ago
overflow register implemented for FTU rate counter
File size: 7.3 KB
Line 
1--------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 12.07.2010
6-- Design Name:
7-- Module Name: FTU_top_tb.vhd
8-- Project Name:
9-- Target Device:
10-- Tool versions:
11-- Description: Testbench for top level entity of FACT FTU board
12--
13-- VHDL Test Bench Created by ISE for module: FTU_top
14--
15-- Dependencies:
16--
17-- Revision:
18-- Revision 0.01 - File Created
19-- Additional Comments:
20--
21-- Notes:
22-- This testbench has been automatically generated using types std_logic and
23-- std_logic_vector for the ports of the unit under test. Xilinx recommends
24-- that these types always be used for the top-level I/O of a design in order
25-- to guarantee that the testbench will bind correctly to the post-implementation
26-- simulation model.
27--------------------------------------------------------------------------------
28library IEEE;
29use IEEE.STD_LOGIC_1164.ALL;
30use IEEE.STD_LOGIC_UNSIGNED.ALL;
31use IEEE.NUMERIC_STD.ALL;
32
33library UNISIM;
34use UNISIM.VComponents.all;
35
36entity FTU_top_tb is
37end FTU_top_tb;
38
39architecture behavior of FTU_top_tb is
40
41 -- Component Declaration for the Unit Under Test (UUT)
42
43 component FTU_top
44 port(
45 -- global control
46 ext_clk : IN STD_LOGIC; -- external clock from FTU board
47 brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address
48 brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID
49
50 -- rate counters LVDS inputs
51 -- use IBUFDS differential input buffer
52 patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch
53 patch_A_n : IN STD_LOGIC;
54 patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch
55 patch_B_n : IN STD_LOGIC;
56 patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch
57 patch_C_n : IN STD_LOGIC;
58 patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch
59 patch_D_n : IN STD_LOGIC;
60 trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit
61 trig_prim_n : IN STD_LOGIC;
62
63 -- DAC interface
64 sck : OUT STD_LOGIC; -- serial clock to DAC
65 mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in
66 clr : OUT STD_LOGIC; -- clear signal to DAC
67 cs_ld : OUT STD_LOGIC; -- chip select or load to DAC
68
69 -- RS-485 interface to FTM
70 rx : IN STD_LOGIC; -- serial data from FTM
71 tx : OUT STD_LOGIC; -- serial data to FTM
72 rx_en : OUT STD_LOGIC; -- enable RS-485 receiver
73 tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter
74
75 -- analog buffer enable
76 enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
77 enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
78 enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
79 enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
80
81 -- testpoints
82 TP_A : OUT STD_LOGIC_VECTOR(11 downto 0) -- testpoints
83 );
84 end component;
85
86 --Inputs
87 signal ext_clk : STD_LOGIC := '0';
88 signal brd_add : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
89 signal brd_id : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
90 signal patch_A_p : STD_LOGIC := '0';
91 signal patch_A_n : STD_LOGIC := '0';
92 signal patch_B_p : STD_LOGIC := '0';
93 signal patch_B_n : STD_LOGIC := '0';
94 signal patch_C_p : STD_LOGIC := '0';
95 signal patch_C_n : STD_LOGIC := '0';
96 signal patch_D_p : STD_LOGIC := '0';
97 signal patch_D_n : STD_LOGIC := '0';
98 signal trig_prim_p : STD_LOGIC := '0';
99 signal trig_prim_n : STD_LOGIC := '0';
100 signal rx : STD_LOGIC := '0';
101
102 --Outputs
103 signal enables_A : STD_LOGIC_VECTOR(8 downto 0);
104 signal enables_B : STD_LOGIC_VECTOR(8 downto 0);
105 signal enables_C : STD_LOGIC_VECTOR(8 downto 0);
106 signal enables_D : STD_LOGIC_VECTOR(8 downto 0);
107 signal clr : STD_LOGIC;
108 signal cs_ld : STD_LOGIC;
109 signal sck : STD_LOGIC;
110 signal mosi : STD_LOGIC;
111 signal tx : STD_LOGIC;
112 signal rx_en : STD_LOGIC;
113 signal tx_en : STD_LOGIC;
114 signal TP_A : STD_LOGIC_VECTOR(11 downto 0);
115
116 --single-ended trigger signals
117 signal patch_A_sig : STD_LOGIC := '0';
118 signal patch_B_sig : STD_LOGIC := '0';
119 signal patch_C_sig : STD_LOGIC := '0';
120 signal patch_D_sig : STD_LOGIC := '0';
121 signal trigger_sig : STD_LOGIC := '0';
122
123 -- Clock period definitions
124 constant ext_clk_period : TIME := 20 ns;
125
126begin
127
128 -- Instantiate the Unit Under Test (UUT)
129 uut: FTU_top
130 port map(
131 ext_clk => ext_clk,
132 brd_add => brd_add,
133 brd_id => brd_id,
134 patch_A_p => patch_A_p,
135 patch_A_n => patch_A_n,
136 patch_B_p => patch_B_p,
137 patch_B_n => patch_B_n,
138 patch_C_p => patch_C_p,
139 patch_C_n => patch_C_n,
140 patch_D_p => patch_D_p,
141 patch_D_n => patch_D_n,
142 trig_prim_p => trig_prim_p,
143 trig_prim_n => trig_prim_n,
144 rx => rx,
145 rx_en => rx_en,
146 enables_A => enables_A,
147 enables_B => enables_B,
148 enables_C => enables_C,
149 enables_D => enables_D,
150 clr => clr,
151 cs_ld => cs_ld,
152 sck => sck,
153 mosi => mosi,
154 tx => tx,
155 tx_en => tx_en,
156 TP_A => TP_A
157 );
158
159 --differential output buffer for patch A
160 OBUFDS_LVDS_33_A : OBUFDS_LVDS_33
161 port map(
162 O => patch_A_p,
163 OB => patch_A_n,
164 I => patch_A_sig
165 );
166
167 OBUFDS_LVDS_33_B : OBUFDS_LVDS_33
168 port map(
169 O => patch_B_p,
170 OB => patch_B_n,
171 I => patch_B_sig
172 );
173
174 OBUFDS_LVDS_33_C : OBUFDS_LVDS_33
175 port map(
176 O => patch_C_p,
177 OB => patch_C_n,
178 I => patch_C_sig
179 );
180
181 OBUFDS_LVDS_33_D : OBUFDS_LVDS_33
182 port map(
183 O => patch_D_p,
184 OB => patch_D_n,
185 I => patch_D_sig
186 );
187
188 OBUFDS_LVDS_33_t : OBUFDS_LVDS_33
189 port map(
190 O => trig_prim_p,
191 OB => trig_prim_n,
192 I => trigger_sig
193 );
194
195 -- Clock process definitions
196 ext_clk_proc: process
197 begin
198 ext_clk <= '0';
199 wait for ext_clk_period/2;
200 ext_clk <= '1';
201 wait for ext_clk_period/2;
202 end process ext_clk_proc;
203
204 -- Stimulus process
205 stim_proc: process
206 begin
207 -- FTU not yet initialized
208 wait for 10us;
209 trigger_sig <= '1';
210 wait for 5ns;
211 trigger_sig <= '0';
212 wait for 99us;
213 trigger_sig <= '1';
214 wait for 5ns;
215 trigger_sig <= '0';
216 wait for 1us;
217 trigger_sig <= '1';
218 wait for 5ns;
219 trigger_sig <= '0';
220 -- now FTU is initialized
221 wait for 4us;
222 trigger_sig <= '1';
223 wait for 5ns;
224 trigger_sig <= '0';
225 wait for 4us;
226 trigger_sig <= '1';
227 wait for 5ns;
228 trigger_sig <= '0';
229 wait for 22us;
230 trigger_sig <= '1';
231 wait for 5ns;
232 trigger_sig <= '0';
233 wait;
234
235 end process stim_proc;
236
237end;
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