source: firmware/FTU/FTU_top_tb.vhd@ 9932

Last change on this file since 9932 was 9928, checked in by weitzel, 15 years ago
first version of RS485 interface added to FTU firmware; not yet connected to main control state machine
File size: 19.8 KB
Line 
1--------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel, P. Vogler
4--
5-- Create Date: 12.07.2010
6-- Design Name:
7-- Module Name: FTU_top_tb.vhd
8-- Project Name:
9-- Target Device:
10-- Tool versions:
11-- Description: Testbench for top level entity of FACT FTU board
12--
13-- VHDL Test Bench Created by ISE for module: FTU_top
14--
15-- Dependencies:
16--
17-- Revision:
18-- Revision 0.01 - File Created
19-- Additional Comments:
20--
21-- Notes:
22-- This testbench has been automatically generated using types std_logic and
23-- std_logic_vector for the ports of the unit under test. Xilinx recommends
24-- that these types always be used for the top-level I/O of a design in order
25-- to guarantee that the testbench will bind correctly to the post-implementation
26-- simulation model.
27--------------------------------------------------------------------------------
28library IEEE;
29use IEEE.STD_LOGIC_1164.ALL;
30use IEEE.STD_LOGIC_UNSIGNED.ALL;
31use IEEE.NUMERIC_STD.ALL;
32
33library UNISIM;
34use UNISIM.VComponents.all;
35
36entity FTU_top_tb is
37end FTU_top_tb;
38
39architecture behavior of FTU_top_tb is
40
41 -- Component Declaration for the Unit Under Test (UUT)
42
43 component FTU_top
44 port(
45 -- global control
46 ext_clk : IN STD_LOGIC; -- external clock from FTU board
47 brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address
48 brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID
49
50 -- rate counters LVDS inputs
51 -- use IBUFDS differential input buffer
52 patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch
53 patch_A_n : IN STD_LOGIC;
54 patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch
55 patch_B_n : IN STD_LOGIC;
56 patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch
57 patch_C_n : IN STD_LOGIC;
58 patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch
59 patch_D_n : IN STD_LOGIC;
60 trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit
61 trig_prim_n : IN STD_LOGIC;
62
63 -- DAC interface
64 sck : OUT STD_LOGIC; -- serial clock to DAC
65 mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in
66 clr : OUT STD_LOGIC; -- clear signal to DAC
67 cs_ld : OUT STD_LOGIC; -- chip select or load to DAC
68
69 -- RS-485 interface to FTM
70 rx : IN STD_LOGIC; -- serial data from FTM
71 tx : OUT STD_LOGIC; -- serial data to FTM
72 rx_en : OUT STD_LOGIC; -- enable RS-485 receiver
73 tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter
74
75 -- analog buffer enable
76 enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
77 enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
78 enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
79 enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
80
81 -- testpoints
82 TP_A : OUT STD_LOGIC_VECTOR(11 downto 0) -- testpoints
83 );
84 end component;
85
86 --Inputs
87 signal ext_clk : STD_LOGIC := '0';
88 signal brd_add : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
89 signal brd_id : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
90 signal patch_A_p : STD_LOGIC := '0';
91 signal patch_A_n : STD_LOGIC := '0';
92 signal patch_B_p : STD_LOGIC := '0';
93 signal patch_B_n : STD_LOGIC := '0';
94 signal patch_C_p : STD_LOGIC := '0';
95 signal patch_C_n : STD_LOGIC := '0';
96 signal patch_D_p : STD_LOGIC := '0';
97 signal patch_D_n : STD_LOGIC := '0';
98 signal trig_prim_p : STD_LOGIC := '0';
99 signal trig_prim_n : STD_LOGIC := '0';
100 signal rx : STD_LOGIC := '1';
101
102 --Outputs
103 signal enables_A : STD_LOGIC_VECTOR(8 downto 0);
104 signal enables_B : STD_LOGIC_VECTOR(8 downto 0);
105 signal enables_C : STD_LOGIC_VECTOR(8 downto 0);
106 signal enables_D : STD_LOGIC_VECTOR(8 downto 0);
107 signal clr : STD_LOGIC;
108 signal cs_ld : STD_LOGIC;
109 signal sck : STD_LOGIC;
110 signal mosi : STD_LOGIC;
111 signal tx : STD_LOGIC;
112 signal rx_en : STD_LOGIC;
113 signal tx_en : STD_LOGIC;
114 signal TP_A : STD_LOGIC_VECTOR(11 downto 0);
115
116 --single-ended trigger signals
117 signal patch_A_sig : STD_LOGIC := '0';
118 signal patch_B_sig : STD_LOGIC := '0';
119 signal patch_C_sig : STD_LOGIC := '0';
120 signal patch_D_sig : STD_LOGIC := '0';
121 signal trigger_sig : STD_LOGIC := '0';
122
123 -- Clock period definitions
124 constant ext_clk_period : TIME := 20 ns;
125 constant baud_rate_period : TIME := 10 us;
126
127begin
128
129 -- Instantiate the Unit Under Test (UUT)
130 uut: FTU_top
131 port map(
132 ext_clk => ext_clk,
133 brd_add => brd_add,
134 brd_id => brd_id,
135 patch_A_p => patch_A_p,
136 patch_A_n => patch_A_n,
137 patch_B_p => patch_B_p,
138 patch_B_n => patch_B_n,
139 patch_C_p => patch_C_p,
140 patch_C_n => patch_C_n,
141 patch_D_p => patch_D_p,
142 patch_D_n => patch_D_n,
143 trig_prim_p => trig_prim_p,
144 trig_prim_n => trig_prim_n,
145 rx => rx,
146 rx_en => rx_en,
147 enables_A => enables_A,
148 enables_B => enables_B,
149 enables_C => enables_C,
150 enables_D => enables_D,
151 clr => clr,
152 cs_ld => cs_ld,
153 sck => sck,
154 mosi => mosi,
155 tx => tx,
156 tx_en => tx_en,
157 TP_A => TP_A
158 );
159
160 --differential output buffer for patch A
161 OBUFDS_LVDS_33_A : OBUFDS_LVDS_33
162 port map(
163 O => patch_A_p,
164 OB => patch_A_n,
165 I => patch_A_sig
166 );
167
168 OBUFDS_LVDS_33_B : OBUFDS_LVDS_33
169 port map(
170 O => patch_B_p,
171 OB => patch_B_n,
172 I => patch_B_sig
173 );
174
175 OBUFDS_LVDS_33_C : OBUFDS_LVDS_33
176 port map(
177 O => patch_C_p,
178 OB => patch_C_n,
179 I => patch_C_sig
180 );
181
182 OBUFDS_LVDS_33_D : OBUFDS_LVDS_33
183 port map(
184 O => patch_D_p,
185 OB => patch_D_n,
186 I => patch_D_sig
187 );
188
189 OBUFDS_LVDS_33_t : OBUFDS_LVDS_33
190 port map(
191 O => trig_prim_p,
192 OB => trig_prim_n,
193 I => trigger_sig
194 );
195
196 -- Clock process definitions
197 ext_clk_proc: process
198 begin
199 ext_clk <= '0';
200 wait for ext_clk_period/2;
201 ext_clk <= '1';
202 wait for ext_clk_period/2;
203 end process ext_clk_proc;
204
205 -- Stimulus process
206 stim_proc: process
207 begin
208 ---------------------------------------------------------------------------
209 -- FTU not yet initialized
210 ---------------------------------------------------------------------------
211 wait for 10us;
212 trigger_sig <= '1';
213 wait for 5ns;
214 trigger_sig <= '0';
215 wait for 99us;
216 trigger_sig <= '1';
217 wait for 5ns;
218 trigger_sig <= '0';
219 wait for 1us;
220 trigger_sig <= '1';
221 wait for 5ns;
222 trigger_sig <= '0';
223 ---------------------------------------------------------------------------
224 -- now FTU is initialized
225 ---------------------------------------------------------------------------
226 wait for 4us;
227 trigger_sig <= '1';
228 wait for 5ns;
229 trigger_sig <= '0';
230 wait for 4us;
231 trigger_sig <= '1';
232 wait for 5ns;
233 trigger_sig <= '0';
234 wait for 22us;
235 trigger_sig <= '1';
236 wait for 5ns;
237 trigger_sig <= '0';
238 ---------------------------------------------------------------------------
239 -- test now RS485
240 ---------------------------------------------------------------------------
241 wait for 100us;
242 rx <= '0'; --start bit
243 wait for baud_rate_period;
244 rx <= '0'; --start delimiter bit 0
245 wait for baud_rate_period;
246 rx <= '0'; --start delimiter bit 1
247 wait for baud_rate_period;
248 rx <= '0'; --start delimiter bit 2
249 wait for baud_rate_period;
250 rx <= '0'; --start delimiter bit 3
251 wait for baud_rate_period;
252 rx <= '0'; --start delimiter bit 4
253 wait for baud_rate_period;
254 rx <= '0'; --start delimiter bit 5
255 wait for baud_rate_period;
256 rx <= '1'; --start delimiter bit 6
257 wait for baud_rate_period;
258 rx <= '0'; --start delimiter bit 7
259 wait for baud_rate_period;
260 rx <= '1'; --stop bit
261 wait for baud_rate_period;
262 rx <= '1'; --stop bit
263 wait for baud_rate_period;
264 ---------------------------------------------------------------------------
265 wait for 1us;
266 rx <= '0'; --start bit
267 wait for baud_rate_period;
268 rx <= '0'; --FTU address bit 0
269 wait for baud_rate_period;
270 rx <= '0'; --FTU address bit 1
271 wait for baud_rate_period;
272 rx <= '0'; --FTU address bit 2
273 wait for baud_rate_period;
274 rx <= '0'; --FTU address bit 3
275 wait for baud_rate_period;
276 rx <= '0'; --FTU address bit 4
277 wait for baud_rate_period;
278 rx <= '0'; --FTU address bit 5
279 wait for baud_rate_period;
280 rx <= '0'; --FTU address bit 6
281 wait for baud_rate_period;
282 rx <= '0'; --FTU address bit 7
283 wait for baud_rate_period;
284 rx <= '1'; --stop bit
285 wait for baud_rate_period;
286 rx <= '1'; --stop bit
287 wait for baud_rate_period;
288 ---------------------------------------------------------------------------
289 wait for 10ns;
290 rx <= '0'; --start bit
291 wait for baud_rate_period;
292 rx <= '0'; --FTM address bit 0
293 wait for baud_rate_period;
294 rx <= '0'; --FTM address bit 1
295 wait for baud_rate_period;
296 rx <= '0'; --FTM address bit 2
297 wait for baud_rate_period;
298 rx <= '0'; --FTM address bit 3
299 wait for baud_rate_period;
300 rx <= '0'; --FTM address bit 4
301 wait for baud_rate_period;
302 rx <= '0'; --FTM address bit 5
303 wait for baud_rate_period;
304 rx <= '1'; --FTM address bit 6
305 wait for baud_rate_period;
306 rx <= '1'; --FTM address bit 7
307 wait for baud_rate_period;
308 rx <= '1'; --stop bit
309 wait for baud_rate_period;
310 rx <= '1'; --stop bit
311 wait for baud_rate_period;
312 ---------------------------------------------------------------------------
313 wait for 100ns;
314 rx <= '0'; --start bit
315 wait for baud_rate_period;
316 rx <= '0'; --instruction bit 0
317 wait for baud_rate_period;
318 rx <= '1'; --instruction bit 1
319 wait for baud_rate_period;
320 rx <= '0'; --instruction bit 2
321 wait for baud_rate_period;
322 rx <= '0'; --instruction bit 3
323 wait for baud_rate_period;
324 rx <= '0'; --instruction bit 4
325 wait for baud_rate_period;
326 rx <= '0'; --instruction bit 5
327 wait for baud_rate_period;
328 rx <= '0'; --instruction bit 6
329 wait for baud_rate_period;
330 rx <= '0'; --instruction bit 7
331 wait for baud_rate_period;
332 rx <= '1'; --stop bit
333 wait for baud_rate_period;
334 rx <= '1'; --stop bit
335 wait for baud_rate_period;
336 ---------------------------------------------------------------------------
337 wait for 200us;
338 rx <= '0'; --start bit
339 wait for baud_rate_period;
340 rx <= '0'; --data1 bit 0
341 wait for baud_rate_period;
342 rx <= '0'; --data1 bit 1
343 wait for baud_rate_period;
344 rx <= '0'; --data1 bit 2
345 wait for baud_rate_period;
346 rx <= '0'; --data1 bit 3
347 wait for baud_rate_period;
348 rx <= '0'; --data1 bit 4
349 wait for baud_rate_period;
350 rx <= '0'; --data1 bit 5
351 wait for baud_rate_period;
352 rx <= '0'; --data1 bit 6
353 wait for baud_rate_period;
354 rx <= '0'; --data1 bit 7
355 wait for baud_rate_period;
356 rx <= '1'; --stop bit
357 wait for baud_rate_period;
358 rx <= '1'; --stop bit
359 wait for baud_rate_period;
360 ---------------------------------------------------------------------------
361 wait for 100ns;
362 rx <= '0'; --start bit
363 wait for baud_rate_period;
364 rx <= '0'; --data2 bit 0
365 wait for baud_rate_period;
366 rx <= '0'; --data2 bit 1
367 wait for baud_rate_period;
368 rx <= '0'; --data2 bit 2
369 wait for baud_rate_period;
370 rx <= '0'; --data2 bit 3
371 wait for baud_rate_period;
372 rx <= '0'; --data2 bit 4
373 wait for baud_rate_period;
374 rx <= '0'; --data2 bit 5
375 wait for baud_rate_period;
376 rx <= '0'; --data2 bit 6
377 wait for baud_rate_period;
378 rx <= '0'; --data2 bit 7
379 wait for baud_rate_period;
380 rx <= '1'; --stop bit
381 wait for baud_rate_period;
382 rx <= '1'; --stop bit
383 wait for baud_rate_period;
384 ---------------------------------------------------------------------------
385 wait for 100ns;
386 rx <= '0'; --start bit
387 wait for baud_rate_period;
388 rx <= '0'; --data3 bit 0
389 wait for baud_rate_period;
390 rx <= '0'; --data3 bit 1
391 wait for baud_rate_period;
392 rx <= '0'; --data3 bit 2
393 wait for baud_rate_period;
394 rx <= '0'; --data3 bit 3
395 wait for baud_rate_period;
396 rx <= '0'; --data3 bit 4
397 wait for baud_rate_period;
398 rx <= '0'; --data3 bit 5
399 wait for baud_rate_period;
400 rx <= '0'; --data3 bit 6
401 wait for baud_rate_period;
402 rx <= '0'; --data3 bit 7
403 wait for baud_rate_period;
404 rx <= '1'; --stop bit
405 wait for baud_rate_period;
406 rx <= '1'; --stop bit
407 wait for baud_rate_period;
408 ---------------------------------------------------------------------------
409 wait for 100ns;
410 rx <= '0'; --start bit
411 wait for baud_rate_period;
412 rx <= '0'; --data4 bit 0
413 wait for baud_rate_period;
414 rx <= '0'; --data4 bit 1
415 wait for baud_rate_period;
416 rx <= '0'; --data4 bit 2
417 wait for baud_rate_period;
418 rx <= '0'; --data4 bit 3
419 wait for baud_rate_period;
420 rx <= '0'; --data4 bit 4
421 wait for baud_rate_period;
422 rx <= '0'; --data4 bit 5
423 wait for baud_rate_period;
424 rx <= '0'; --data4 bit 6
425 wait for baud_rate_period;
426 rx <= '0'; --data4 bit 7
427 wait for baud_rate_period;
428 rx <= '1'; --stop bit
429 wait for baud_rate_period;
430 rx <= '1'; --stop bit
431 wait for baud_rate_period;
432 ---------------------------------------------------------------------------
433 wait for 100ns;
434 rx <= '0'; --start bit
435 wait for baud_rate_period;
436 rx <= '0'; --data5 bit 0
437 wait for baud_rate_period;
438 rx <= '0'; --data5 bit 1
439 wait for baud_rate_period;
440 rx <= '0'; --data5 bit 2
441 wait for baud_rate_period;
442 rx <= '0'; --data5 bit 3
443 wait for baud_rate_period;
444 rx <= '0'; --data5 bit 4
445 wait for baud_rate_period;
446 rx <= '0'; --data5 bit 5
447 wait for baud_rate_period;
448 rx <= '0'; --data5 bit 6
449 wait for baud_rate_period;
450 rx <= '0'; --data5 bit 7
451 wait for baud_rate_period;
452 rx <= '1'; --stop bit
453 wait for baud_rate_period;
454 rx <= '1'; --stop bit
455 wait for baud_rate_period;
456 ---------------------------------------------------------------------------
457 wait for 100ns;
458 rx <= '0'; --start bit
459 wait for baud_rate_period;
460 rx <= '0'; --data6 bit 0
461 wait for baud_rate_period;
462 rx <= '0'; --data6 bit 1
463 wait for baud_rate_period;
464 rx <= '0'; --data6 bit 2
465 wait for baud_rate_period;
466 rx <= '0'; --data6 bit 3
467 wait for baud_rate_period;
468 rx <= '0'; --data6 bit 4
469 wait for baud_rate_period;
470 rx <= '0'; --data6 bit 5
471 wait for baud_rate_period;
472 rx <= '0'; --data6 bit 6
473 wait for baud_rate_period;
474 rx <= '0'; --data6 bit 7
475 wait for baud_rate_period;
476 rx <= '1'; --stop bit
477 wait for baud_rate_period;
478 rx <= '1'; --stop bit
479 wait for baud_rate_period;
480 ---------------------------------------------------------------------------
481 wait for 100ns;
482 rx <= '0'; --start bit
483 wait for baud_rate_period;
484 rx <= '0'; --data7 bit 0
485 wait for baud_rate_period;
486 rx <= '0'; --data7 bit 1
487 wait for baud_rate_period;
488 rx <= '0'; --data7 bit 2
489 wait for baud_rate_period;
490 rx <= '0'; --data7 bit 3
491 wait for baud_rate_period;
492 rx <= '0'; --data7 bit 4
493 wait for baud_rate_period;
494 rx <= '0'; --data7 bit 5
495 wait for baud_rate_period;
496 rx <= '0'; --data7 bit 6
497 wait for baud_rate_period;
498 rx <= '0'; --data7 bit 7
499 wait for baud_rate_period;
500 rx <= '1'; --stop bit
501 wait for baud_rate_period;
502 rx <= '1'; --stop bit
503 wait for baud_rate_period;
504 ---------------------------------------------------------------------------
505 wait for 100ns;
506 rx <= '0'; --start bit
507 wait for baud_rate_period;
508 rx <= '0'; --data8 bit 0
509 wait for baud_rate_period;
510 rx <= '0'; --data8 bit 1
511 wait for baud_rate_period;
512 rx <= '0'; --data8 bit 2
513 wait for baud_rate_period;
514 rx <= '0'; --data8 bit 3
515 wait for baud_rate_period;
516 rx <= '0'; --data8 bit 4
517 wait for baud_rate_period;
518 rx <= '0'; --data8 bit 5
519 wait for baud_rate_period;
520 rx <= '0'; --data8 bit 6
521 wait for baud_rate_period;
522 rx <= '0'; --data8 bit 7
523 wait for baud_rate_period;
524 rx <= '1'; --stop bit
525 wait for baud_rate_period;
526 rx <= '1'; --stop bit
527 wait for baud_rate_period;
528 ---------------------------------------------------------------------------
529 wait for 100ns;
530 rx <= '0'; --start bit
531 wait for baud_rate_period;
532 rx <= '0'; --data9 bit 0
533 wait for baud_rate_period;
534 rx <= '0'; --data9 bit 1
535 wait for baud_rate_period;
536 rx <= '0'; --data9 bit 2
537 wait for baud_rate_period;
538 rx <= '0'; --data9 bit 3
539 wait for baud_rate_period;
540 rx <= '0'; --data9 bit 4
541 wait for baud_rate_period;
542 rx <= '0'; --data9 bit 5
543 wait for baud_rate_period;
544 rx <= '0'; --data9 bit 6
545 wait for baud_rate_period;
546 rx <= '0'; --data9 bit 7
547 wait for baud_rate_period;
548 rx <= '1'; --stop bit
549 wait for baud_rate_period;
550 rx <= '1'; --stop bit
551 wait for baud_rate_period;
552 ---------------------------------------------------------------------------
553 wait for 100ns;
554 rx <= '0'; --start bit
555 wait for baud_rate_period;
556 rx <= '0'; --data10 bit 0
557 wait for baud_rate_period;
558 rx <= '0'; --data10 bit 1
559 wait for baud_rate_period;
560 rx <= '0'; --data10 bit 2
561 wait for baud_rate_period;
562 rx <= '0'; --data10 bit 3
563 wait for baud_rate_period;
564 rx <= '0'; --data10 bit 4
565 wait for baud_rate_period;
566 rx <= '0'; --data10 bit 5
567 wait for baud_rate_period;
568 rx <= '0'; --data10 bit 6
569 wait for baud_rate_period;
570 rx <= '0'; --data10 bit 7
571 wait for baud_rate_period;
572 rx <= '1'; --stop bit
573 wait for baud_rate_period;
574 rx <= '1'; --stop bit
575 wait for baud_rate_period;
576 ---------------------------------------------------------------------------
577 wait for 100ns;
578 rx <= '0'; --start bit
579 wait for baud_rate_period;
580 rx <= '0'; --data11 bit 0
581 wait for baud_rate_period;
582 rx <= '0'; --data11 bit 1
583 wait for baud_rate_period;
584 rx <= '0'; --data11 bit 2
585 wait for baud_rate_period;
586 rx <= '0'; --data11 bit 3
587 wait for baud_rate_period;
588 rx <= '0'; --data11 bit 4
589 wait for baud_rate_period;
590 rx <= '0'; --data11 bit 5
591 wait for baud_rate_period;
592 rx <= '0'; --data11 bit 6
593 wait for baud_rate_period;
594 rx <= '0'; --data11 bit 7
595 wait for baud_rate_period;
596 rx <= '1'; --stop bit
597 wait for baud_rate_period;
598 rx <= '1'; --stop bit
599 wait for baud_rate_period;
600 ---------------------------------------------------------------------------
601 wait for 100ns;
602 rx <= '0'; --start bit
603 wait for baud_rate_period;
604 rx <= '0'; --check sum bit 0
605 wait for baud_rate_period;
606 rx <= '0'; --check sum bit 1
607 wait for baud_rate_period;
608 rx <= '0'; --check sum bit 2
609 wait for baud_rate_period;
610 rx <= '0'; --check sum bit 3
611 wait for baud_rate_period;
612 rx <= '0'; --check sum bit 4
613 wait for baud_rate_period;
614 rx <= '0'; --check sum bit 5
615 wait for baud_rate_period;
616 rx <= '0'; --check sum bit 6
617 wait for baud_rate_period;
618 rx <= '0'; --check sum bit 7
619 wait for baud_rate_period;
620 rx <= '1'; --stop bit
621 wait for baud_rate_period;
622 rx <= '1'; --stop bit
623 wait for baud_rate_period;
624 ---------------------------------------------------------------------------
625 rx <= '1';
626 wait;
627
628 end process stim_proc;
629
630end;
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