source: firmware/FTU/clock/FTU_clk_gen.vhd@ 17370

Last change on this file since 17370 was 10037, checked in by weitzel, 14 years ago
FTU counter changed from 16 to 30 bit
File size: 2.9 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: Q. Weitzel
4--
5-- Create Date: 14:09:39 07/12/2010
6-- Design Name:
7-- Module Name: FTU_clk_gen - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: interface to different DCMs and clk dividers for FTU board
12-- add here more DCMs if needed
13--
14-- Dependencies:
15--
16-- Revision:
17-- Revision 0.01 - File Created
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21library IEEE;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.STD_LOGIC_ARITH.ALL;
24use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
26---- Uncomment the following library declaration if instantiating
27---- any Xilinx primitives in this code.
28--library UNISIM;
29--use UNISIM.VComponents.all;
30
31entity FTU_clk_gen is
32 Port (
33 clk : IN STD_LOGIC;
34 rst : IN STD_LOGIC;
35 clk_50 : OUT STD_LOGIC;
36 clk_1 : OUT STD_LOGIC;
37 ready : OUT STD_LOGIC
38 );
39end FTU_clk_gen;
40
41architecture Behavioral of FTU_clk_gen is
42
43 component FTU_dcm_50M_to_50M
44 port (
45 CLKIN_IN : in std_logic;
46 RST_IN : in std_logic;
47 CLKFX_OUT : out std_logic;
48 CLKIN_IBUFG_OUT : out std_logic;
49 LOCKED_OUT : out std_logic);
50 end component;
51
52 component Clock_Divider
53 port(
54 clock_in : IN STD_LOGIC;
55 clock_out : OUT STD_LOGIC
56 );
57 end component;
58
59 signal clk_1M_sig : std_logic;
60 signal clk_50M_sig : std_logic;
61
62begin
63
64 Inst_FTU_dcm_50M_to_50M : FTU_dcm_50M_to_50M
65 port map(
66 CLKIN_IN => clk,
67 RST_IN => rst,
68 CLKFX_OUT => clk_50M_sig,
69 CLKIN_IBUFG_OUT => open,
70 LOCKED_OUT => ready
71 );
72
73 Inst_Clock_Divider : Clock_Divider
74 port map (
75 clock_in => clk_50M_sig,
76 clock_out => clk_1M_sig
77 );
78
79 clk_50 <= clk_50M_sig;
80 clk_1 <= clk_1M_sig;
81
82end Behavioral;
83
84----------------------------------------------------------------------------------
85
86library IEEE;
87use IEEE.STD_LOGIC_1164.ALL;
88use IEEE.STD_LOGIC_ARITH.ALL;
89use IEEE.STD_LOGIC_UNSIGNED.ALL;
90
91library ftu_definitions;
92USE ftu_definitions.ftu_array_types.all;
93USE ftu_definitions.ftu_constants.all;
94
95entity Clock_Divider is
96 generic(
97 divider : integer := INT_CLK_FREQUENCY / COUNTER_FREQUENCY
98 );
99 port(
100 clock_in : in std_logic;
101 clock_out : out std_logic := '0'
102 );
103end entity Clock_Divider;
104
105architecture RTL of Clock_Divider is
106
107begin
108
109 process (clock_in)
110 variable Z: integer range 0 to divider - 1;
111 begin
112 if rising_edge(clock_in) then
113 if (Z < divider - 1) then
114 Z := Z + 1;
115 else
116 Z := 0;
117 end if;
118 if (Z = 0) then
119 clock_out <= '1';
120 end if;
121 if (Z = divider / 2) then
122 clock_out <= '0';
123 end if;
124 end if;
125 end process;
126
127end architecture RTL;
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