source: firmware/FTU/ftu_board.ucf @ 11756

Last change on this file since 11756 was 10037, checked in by weitzel, 9 years ago
FTU counter changed from 16 to 30 bit
File size: 7.8 KB
Line 
1########################################################
2# FTU Board
3# FACT Trigger Unit
4#
5# Pin location constraints
6#
7# by Patrick Vogler, Quirin Weitzel
8# 11 August 2010
9########################################################
10
11
12#Clock
13#######################################################
14NET ext_clk LOC = Y11 | IOSTANDARD=LVCMOS33; # Clk     
15
16
17# RS-485 Interface
18#######################################################
19NET rx_en LOC  = T20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_RE: enable RS-485 receiver             
20NET tx_en LOC  = U20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DE: enable RS-485 transmitter           
21NET tx    LOC  = U19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DO: serial data to FTM         
22NET rx    LOC  = R20 | IOSTANDARD=LVCMOS33;               # 485_DI: serial data from FTM
23
24
25# Board ID - inputs
26# local board-ID "solder programmable"
27#######################################################
28#NET brd_id<0> LOC  = C4 | IOSTANDARD=LVCMOS33; # P0           
29#NET brd_id<1> LOC  = C5 | IOSTANDARD=LVCMOS33; # P1           
30#NET brd_id<2> LOC  = C6 | IOSTANDARD=LVCMOS33; # P2           
31#NET brd_id<3> LOC  = C7 | IOSTANDARD=LVCMOS33; # P3           
32#NET brd_id<4> LOC  = C8 | IOSTANDARD=LVCMOS33; # P4           
33#NET brd_id<5> LOC  = B8 | IOSTANDARD=LVCMOS33; # P5           
34#NET brd_id<6> LOC  = C9 | IOSTANDARD=LVCMOS33; # P6   
35#NET brd_id<7> LOC  = B9 | IOSTANDARD=LVCMOS33; # P7   
36
37
38# Board Addresses
39# geographical slot address
40#######################################################
41NET brd_add<0> LOC  = A15 | IOSTANDARD=LVCMOS33; # ADDR0
42NET brd_add<1> LOC  = B15 | IOSTANDARD=LVCMOS33; # ADDR1
43NET brd_add<2> LOC  = A16 | IOSTANDARD=LVCMOS33; # ADDR2
44NET brd_add<3> LOC  = A17 | IOSTANDARD=LVCMOS33; # ADDR3
45NET brd_add<4> LOC  = A18 | IOSTANDARD=LVCMOS33; # ADDR4
46NET brd_add<5> LOC  = B18 | IOSTANDARD=LVCMOS33; # ADDR5
47
48
49# DAC SPI Interface
50#######################################################
51NET mosi   LOC  = E20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #MOSI: serial data to DAC, master-out-slave-in               
52NET sck    LOC  = E19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #SCK: serial clock to DAC                   
53NET cs_ld  LOC  = E18 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CS: chip select or load to DAC                 
54NET clr    LOC  = D20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CRL: clear signal to DAC       
55
56
57# Testpoints
58######################################################
59# on Connector J5
60NET TP_A<0> LOC  = B3 | IOSTANDARD=LVCMOS33;  # TP0_0
61NET TP_A<1> LOC  = A3 | IOSTANDARD=LVCMOS33;  # TP1_0
62NET TP_A<2> LOC  = A4 | IOSTANDARD=LVCMOS33;  # TP2_0
63NET TP_A<3> LOC  = B5 | IOSTANDARD=LVCMOS33;  # TP2_0
64
65# on Connector J6
66NET TP_A<4> LOC  = A5 | IOSTANDARD=LVCMOS33;  # TP4_0
67NET TP_A<5> LOC  = A6 | IOSTANDARD=LVCMOS33;  # TP5_0
68NET TP_A<6> LOC  = B7 | IOSTANDARD=LVCMOS33;  # TP6_0
69NET TP_A<7> LOC  = A7 | IOSTANDARD=LVCMOS33;  # TP7_0
70
71# on Connector J7
72NET TP_A<8>  LOC  = B11  | IOSTANDARD=LVCMOS33;  # TP8_0
73NET TP_A<9>  LOC  = A12  | IOSTANDARD=LVCMOS33;  # TP9_0
74NET TP_A<10> LOC  = B12  | IOSTANDARD=LVCMOS33;  # TP10_0
75NET TP_A<11> LOC  = A14  | IOSTANDARD=LVCMOS33;  # TP11_0
76
77
78# Rate counter LVDS Inputs
79######################################################
80# logic signal from first trigger patch
81NET patch_A_p  LOC  = Y4 | IOSTANDARD=LVDS_33 | CLOCK_DEDICATED_ROUTE=FALSE | DIFF_TERM="False"; # LVDS0_P
82NET patch_A_n  LOC  = Y5 | IOSTANDARD=LVDS_33 | CLOCK_DEDICATED_ROUTE=FALSE | DIFF_TERM="False"; # LVDS0_N
83#NET patch_A_p  LOC  = Y4 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # LVDS0_P
84#NET patch_A_n  LOC  = Y5 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # LVDS0_N
85
86# logic signal from second trigger patch
87NET patch_B_p  LOC  = Y6 | IOSTANDARD=LVDS_33 | CLOCK_DEDICATED_ROUTE=FALSE | DIFF_TERM="False"; # LVDS1_P
88NET patch_B_n  LOC  = Y7 | IOSTANDARD=LVDS_33 | CLOCK_DEDICATED_ROUTE=FALSE | DIFF_TERM="False"; # LVDS1_N
89#NET patch_B_p  LOC  = Y6 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # LVDS1_P
90#NET patch_B_n  LOC  = Y7 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # LVDS1_N
91
92# logic signal from third trigger patch
93NET patch_C_p  LOC  = Y17 | IOSTANDARD=LVDS_33 | CLOCK_DEDICATED_ROUTE=FALSE | DIFF_TERM="False" ; # LVDS2_P
94NET patch_C_n  LOC  = Y18 | IOSTANDARD=LVDS_33 | CLOCK_DEDICATED_ROUTE=FALSE | DIFF_TERM="False" ; # LVDS2_N
95#NET patch_C_p  LOC  = Y17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # LVDS2_P
96#NET patch_C_n  LOC  = Y18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # LVDS2_N
97
98# logic signal from fourth trigger patch
99NET patch_D_p  LOC  = Y16 | IOSTANDARD=LVDS_33 | CLOCK_DEDICATED_ROUTE=FALSE | DIFF_TERM="False" ; # LVDS3_P
100NET patch_D_n  LOC  = W16 | IOSTANDARD=LVDS_33 | CLOCK_DEDICATED_ROUTE=FALSE | DIFF_TERM="False" ; # LVDS3_N
101#NET patch_D_p  LOC  = Y16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # LVDS3_P
102#NET patch_D_n  LOC  = W16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # LVDS3_N
103
104#The Trigger Primitive: logic signal from n-out-of-4 circuit
105NET trig_prim_p   LOC  = Y13 | IOSTANDARD=LVDS_33 | CLOCK_DEDICATED_ROUTE=FALSE | DIFF_TERM="False" ; # TRG_P+
106NET trig_prim_n   LOC  = W13 | IOSTANDARD=LVDS_33 | CLOCK_DEDICATED_ROUTE=FALSE | DIFF_TERM="False" ; # TRG_P-
107#NET trig_prim_p   LOC  = Y13 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TRG_P+
108#NET trig_prim_n   LOC  = W13 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TRG_P-
109
110# Enables
111######################################################
112# Patch 0
113NET enables_A<0>  LOC  = D2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_0
114NET enables_A<1>  LOC  = B1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_1
115NET enables_A<2>  LOC  = C2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_2
116NET enables_A<3>  LOC  = D1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_3
117NET enables_A<4>  LOC  = C1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_4
118NET enables_A<5>  LOC  = D4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_5
119NET enables_A<6>  LOC  = E1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_6
120NET enables_A<7>  LOC  = D3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_7
121NET enables_A<8>  LOC  = E3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_8 
122
123## Patch 1
124NET enables_B<0>  LOC  = F2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_0
125NET enables_B<1>  LOC  = F4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_1
126NET enables_B<2>  LOC  = F3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_2
127NET enables_B<3>  LOC  = F1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_3
128NET enables_B<4>  LOC  = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_4
129NET enables_B<5>  LOC  = G4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_5
130NET enables_B<6>  LOC  = H2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_6
131NET enables_B<7>  LOC  = H3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_7
132NET enables_B<8>  LOC  = J3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_8
133
134# Patch 2
135NET enables_C<0>   LOC  = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_0
136NET enables_C<1>   LOC  = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_1
137NET enables_C<2>   LOC  = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_2
138NET enables_C<3>   LOC  = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_3
139NET enables_C<4>   LOC  = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_4
140NET enables_C<5>   LOC  = N3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_5
141NET enables_C<6>   LOC  = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_6
142NET enables_C<7>   LOC  = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_7
143NET enables_C<8>   LOC  = T2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_8
144
145# Patch 3
146NET enables_D<0>   LOC  = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
147NET enables_D<1>   LOC  = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
148NET enables_D<2>   LOC  = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
149NET enables_D<3>   LOC  = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
150NET enables_D<4>   LOC  = U3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
151NET enables_D<5>   LOC  = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
152NET enables_D<6>   LOC  = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
153NET enables_D<7>   LOC  = W1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
154NET enables_D<8>   LOC  = W2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
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