| 1 | ----------------------------------------------------------------------------------
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| 2 | -- Company: ETH Zurich, Institute for Particle Physics
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| 3 | -- Engineer: Q. Weitzel
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| 4 | --
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| 5 | -- Create Date: July 2010
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| 6 | -- Design Name:
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| 7 | -- Module Name: ftu_definitions
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| 8 | -- Project Name:
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| 9 | -- Target Devices:
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| 10 | -- Tool versions:
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| 11 | -- Description: library file for FTU design
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| 12 | --
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| 13 | -- Dependencies:
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| 14 | --
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| 15 | -- Revision:
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| 16 | -- Revision 0.01 - File Created
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| 17 | -- Revision 0.02 - New package "ftu_constants" added, Aug 2010, Q. Weitzel
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| 18 | -- Additional Comments:
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| 19 | --
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| 20 | ----------------------------------------------------------------------------------
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| 21 |
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| 22 |
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| 23 | library IEEE;
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| 24 | use IEEE.STD_LOGIC_1164.all;
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| 25 | use IEEE.STD_LOGIC_ARITH.ALL;
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| 26 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
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| 27 | -- use IEEE.NUMERIC_STD.ALL;
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| 28 |
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| 29 | package ftu_array_types is
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| 30 |
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| 31 | --enable signals to switch on/off pixels in trigger (9 pixels per patch)
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| 32 | type enable_array_type is array (0 to 3) of std_logic_vector(15 downto 0);
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| 33 | constant DEFAULT_ENABLE : enable_array_type := ("0000000111111111", --patch A
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| 34 | "0000000111111111", --patch B
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| 35 | "0000000111111111", --patch C
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| 36 | "0000000111111111");--patch D
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| 37 |
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| 38 | --DAC values to steer trigger thresholds, 12bit octal DAC, 2.5V reference voltage
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| 39 | --First 4 values: patches A-D, DACs 5-7 not used, last value: majority coincidence
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| 40 | type dac_array_type is array (0 to 7) of integer range 0 to 2**12 - 1;
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| 41 | constant DEFAULT_DAC : dac_array_type := (500, 500, 500, 500, 0, 0, 0, 100);
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| 42 |
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| 43 | --array to hold current values of rate counters (as integers)
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| 44 | type rate_array_type is array (0 to 4) of integer range 0 to 2**16 - 1;
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| 45 |
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| 46 | end ftu_array_types;
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| 47 |
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| 48 |
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| 49 | library IEEE;
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| 50 | use IEEE.STD_LOGIC_1164.all;
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| 51 | use IEEE.STD_LOGIC_ARITH.ALL;
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| 52 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
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| 53 | -- use IEEE.NUMERIC_STD.ALL;
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| 54 |
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| 55 | package ftu_constants is
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| 56 |
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| 57 | --internal FPGA clock frequency and rate counter frequency
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| 58 | constant INT_CLK_FREQUENCY : integer := 50000000; -- 50MHz
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| 59 | constant COUNTER_FREQUENCY : integer := 1000000; -- has to be smaller than INT_CLK_FREQUENCY
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| 60 | constant CNTR_FREQ_DIVIDER : integer := 50000; -- for simulation, should normally be 1
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| 61 |
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| 62 | --32byte dual-port RAM, port A: 8byte, port B: 16byte
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| 63 | constant RAM_ADDR_WIDTH_A : integer := 5;
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| 64 | constant RAM_ADDR_WIDTH_B : integer := 4;
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| 65 | constant RAM_ADDR_RATIO : integer := 2;
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| 66 |
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| 67 | --normalization time for trigger counters
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| 68 | constant DEFAULT_PRESCALING : integer := 59; --30s integration time
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| 69 |
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| 70 | constant NO_OF_ENABLE : integer := 4;
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| 71 | constant NO_OF_DAC : integer := 8;
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| 72 | constant NO_OF_DAC_NOT_USED : integer := 3;
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| 73 | constant NO_OF_COUNTER : integer := 5;
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| 74 |
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| 75 | --communication with FTM
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| 76 | constant RS485_BAUD_RATE : integer := 100000; -- bits / sec in our case
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| 77 | constant RS485_BLOCK_WIDTH : integer := 128; -- 16 byte protocol
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| 78 | constant RS485_START_DELIM : std_logic_vector(7 downto 0) := "01000000"; -- start delimiter
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| 79 | constant FTM_ADDRESS : std_logic_vector(7 downto 0) := "11000000"; -- 192
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| 80 |
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| 81 | end ftu_constants;
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