source: firmware/FTU/ftu_definitions.vhd @ 10051

Last change on this file since 10051 was 10051, checked in by weitzel, 9 years ago
some code cleaning and more comments for FTU firmware
File size: 3.6 KB
Line 
1----------------------------------------------------------------------------------
2-- Company:        ETH Zurich, Institute for Particle Physics
3-- Engineer:       Q. Weitzel
4--
5-- Create Date:    July 2010
6-- Design Name:   
7-- Module Name:    ftu_definitions
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:    library file for FTU design                                                                         
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Revision 0.02 - New package "ftu_constants" added, Aug 2010, Q. Weitzel
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21
22
23library IEEE;
24use IEEE.STD_LOGIC_1164.all;
25use IEEE.STD_LOGIC_ARITH.ALL;
26use IEEE.STD_LOGIC_UNSIGNED.ALL;
27-- use IEEE.NUMERIC_STD.ALL;
28
29package ftu_array_types is
30
31  --enable signals to switch on/off pixels in trigger (9 pixels per patch)
32  type enable_array_type is array (0 to 3) of std_logic_vector(15 downto 0);
33  constant DEFAULT_ENABLE : enable_array_type := ("0000000111111111", --patch A
34                                                  "0000000111111111", --patch B
35                                                  "0000000111111111", --patch C
36                                                  "0000000111111111");--patch D
37
38  --DAC values to steer trigger thresholds, 12bit octal DAC, 2.5V reference voltage
39  --First 4 values: patches A-D, DACs 5-7 not used, last value: majority coincidence
40  type dac_array_type is array (0 to 7) of integer range 0 to 2**12 - 1;
41  constant DEFAULT_DAC : dac_array_type := (500, 500, 500, 500, 0, 0, 0, 100);
42
43  --array to hold current values of rate counters (as integers)
44  type rate_array_type is array (0 to 4) of integer range 0 to 2**30 - 1;
45 
46end ftu_array_types;
47
48
49library IEEE;
50use IEEE.STD_LOGIC_1164.all;
51use IEEE.STD_LOGIC_ARITH.ALL;
52use IEEE.STD_LOGIC_UNSIGNED.ALL;
53-- use IEEE.NUMERIC_STD.ALL;
54
55package ftu_constants is
56
57  --internal FPGA clock frequency and rate counter frequency
58  constant INT_CLK_FREQUENCY : integer := 50000000;  -- 50MHz
59  constant COUNTER_FREQUENCY : integer :=  1000000;  -- has to be smaller than INT_CLK_FREQUENCY
60  constant CNTR_FREQ_DIVIDER : integer :=    25000;  -- for simulation, should normally be 1
61   
62  --64byte dual-port RAM, port A: 8byte, port B: 16byte
63  constant RAM_ADDR_WIDTH_A : integer := 6;
64  constant RAM_ADDR_WIDTH_B : integer := 5;
65  constant RAM_ADDR_RATIO   : integer := 2;
66 
67  --counter extension factor (for RAM)
68  constant RAM_CEF : integer := 2;
69   
70  --normalization time for trigger counters
71  constant DEFAULT_PRESCALING : integer := 59; --30s integration time
72
73  constant NO_OF_ENABLE       : integer := 4;
74  constant NO_OF_DAC          : integer := 8;
75  constant NO_OF_DAC_NOT_USED : integer := 3;
76  constant NO_OF_COUNTER      : integer := 5;
77
78  --communication with FTM
79  constant RS485_BAUD_RATE   : integer := 250000;  -- bits / sec in our case
80  constant RS485_TIMEOUT     : integer := (INT_CLK_FREQUENCY * 2) / 1000;  -- 2ms @ 50MHz (100000 clk periods)
81  constant RS485_BLOCK_WIDTH : integer := 224;     -- 28 byte protocol
82  constant RS485_START_DELIM : std_logic_vector(7 downto 0) := "01000000";  -- start delimiter
83  constant FTM_ADDRESS       : std_logic_vector(7 downto 0) := "11000000";  -- 192
84  constant FIRMWARE_ID       : std_logic_vector(7 downto 0) := "00000001";  -- firmware version
85
86  --CRC setup
87  constant CRC_POLYNOMIAL : std_logic_vector(7 downto 0) := "00000111";  -- 8-CCITT
88  constant CRC_INIT_VALUE : std_logic_vector(7 downto 0) := "11111111";
89 
90  --DNA identifier for simulation
91  constant DNA_FOR_SIM : bit_vector := X"01710000E0000501";
92
93end ftu_constants;
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