source: firmware/FTU/old_design/FTU_top.vhd@ 17333

Last change on this file since 17333 was 250, checked in by qweitzel, 14 years ago
restructuring of FTU code started
File size: 5.0 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 11:59:40 01/19/2010
6-- Design Name:
7-- Module Name: FTU_top - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Top level entity of FACT FTU board
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24
25---- Uncomment the following library declaration if instantiating
26---- any Xilinx primitives in this code.
27--library UNISIM;
28--use UNISIM.VComponents.all;
29
30
31entity FTU_top is
32 port(
33 -- global control
34 ext_clk : IN STD_LOGIC; -- external clock from FTU board
35 brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address
36 brd_id : in STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID
37
38 -- rate counters LVDS inputs
39 -- use IBUFDS differential input buffer
40 patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch
41 patch_A_n : IN STD_LOGIC;
42 patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch
43 patch_B_n : IN STD_LOGIC;
44 patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch
45 patch_C_n : IN STD_LOGIC;
46 patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch
47 patch_D_n : IN STD_LOGIC;
48 trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit
49 trig_prim_n : IN STD_LOGIC;
50
51 -- DAC interface
52 sck : OUT STD_LOGIC; -- serial clock to DAC
53 mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in
54 clr : OUT STD_LOGIC; -- clear signal to DAC
55 cs_ld : OUT STD_LOGIC; -- chip select or load to DAC
56
57 -- RS-485 interface to FTM
58 rx : IN STD_LOGIC; -- serial data from FTM
59 tx : OUT STD_LOGIC; -- serial data to FTM
60 rx_en : OUT STD_LOGIC; -- enable RS-485 receiver
61 tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter
62
63 -- analog buffer enable
64 enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
65 enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
66 enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
67 enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
68
69 -- testpoints
70 TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints
71 );
72end FTU_top;
73
74
75architecture Behavioral of FTU_top is
76
77 component FTU_dac_dcm
78 port(
79 CLKIN_IN : IN STD_LOGIC;
80 RST_IN : IN STD_LOGIC;
81 CLKFX_OUT : OUT STD_LOGIC;
82 CLKIN_IBUFG_OUT : OUT STD_LOGIC;
83 LOCKED_OUT : OUT STD_LOGIC
84 );
85 end component;
86
87 component FTU_dac_control
88 port(
89 clk : IN STD_LOGIC;
90 reset : IN STD_LOGIC;
91 miso : IN STD_LOGIC;
92 clr : OUT STD_LOGIC;
93 mosi : OUT STD_LOGIC;
94 sck : OUT STD_LOGIC;
95 cs_ld : OUT STD_LOGIC
96 );
97 end component;
98
99 signal reset_sig : STD_LOGIC := '0'; -- initialize reset to 0 at power up
100 signal clk_5M_sig : STD_LOGIC;
101
102 type FTU_top_StateType is (Init, Running, Reset);
103 signal FTU_top_State, FTU_top_NextState: FTU_top_StateType;
104
105begin
106
107 Inst_FTU_dac_dcm : FTU_dac_dcm
108 port map(
109 CLKIN_IN => ext_clk,
110 RST_IN => reset_sig,
111 CLKFX_OUT => clk_5M_sig,
112 CLKIN_IBUFG_OUT => open,
113 LOCKED_OUT => open
114 );
115
116 Inst_FTU_dac_control : FTU_dac_control
117 port map(
118 clk => clk_5M_sig,
119 reset => reset_sig,
120 miso => '0',
121 clr => clr,
122 mosi => mosi,
123 sck => sck,
124 cs_ld => cs_ld
125 );
126
127 --FTU main state machine (two-process implementation)
128
129 FTU_top_Registers: process (ext_clk)
130 begin
131 if Rising_edge(ext_clk) then
132 FTU_top_State <= FTU_top_NextState;
133 end if;
134 end process FTU_top_Registers;
135
136 FTU_top_C_logic: process (FTU_top_State)
137 begin
138 FTU_top_NextState <= FTU_top_State;
139 case FTU_top_State is
140 when Init =>
141 reset_sig <= '0';
142 FTU_top_NextState <= Running;
143 when Running =>
144 when Reset =>
145 reset_sig <= '1';
146 FTU_top_NextState <= Init;
147 end case;
148 end process FTU_top_C_logic;
149
150end Behavioral;
151
152--What is missing?
153--UART
154--registers (enables, DAC values etc.)
155--rate counters
156--main state machine for FTU: talks to DAC, reads counters, listens to UART
157
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