source: firmware/FTU/old_design/spi_interface/spi_control_sm_16.vhd@ 16318

Last change on this file since 16318 was 156, checked in by qweitzel, 16 years ago
First check-in of VHDL code for FTU: counters, dcm, spi
File size: 17.0 KB
Line 
1---------------------------------------------------------------------------------------------
2---------------------------------------------------------------------------------------------
3-- File: spi_control_sm_16.vhd
4--
5--
6-- Original file: spi_control_sm.vhd
7--
8-- Created: 8-23-00 ALS
9-- This file contains the overall control of the SPI interface. It generates the slave
10-- select signals and the masks so that the SCK signals output to the SPI bus align properly
11-- with the data. It generates the control signals to the shift register and the receive
12-- data register.
13--
14-- This SPI interface operates on bytes of data. When the START signal from the uC is
15-- asserted the byte-wide data in the SPI transmit register is transmitted on the SPI bus.
16-- When this transfer is complete, the BUSY signal is negated and the START signal is
17-- sampled. If the START signal is still asserted indicating that the uC has put new
18-- data in the SPI transmit register, the data in the transmit register will be transmitted.
19-- Each byte of data received from the SPI bus is captured in the receive register.The uC can
20-- read this data once the BUSY signal has negated.
21--
22-- Revised: 9-6-00 ALS
23-- Revised: 9-12-00 ALS
24-- Revised: 10-17-00 ALS
25-- Revised: 10-19-00 ALS
26-- Revised: 10-27-00 ALS
27-- Revised: 12-12-02 JRH
28
29---------------------------------------------------------------------------------------------
30---------------------------------------------------------------------------------------------
31-- Modified from 8 to 16 bit word size by Patrick Vogler
32-- 18th November 2009
33--
34-- Modifications are marked by: *Mod: <modification>
35--
36-- Cleaned up by Quirin Weitzel
37-- 21th January 2010
38---------------------------------------------------------------------------------------------
39---------------------------------------------------------------------------------------------
40library IEEE;
41use IEEE.std_logic_1164.all;
42use IEEE.std_logic_arith.all;
43
44entity spi_control_sm is
45 port(
46 -- internal uC interface signals
47 start : in std_logic; -- start transfer
48 done : out std_logic; -- byte transfer is complete
49 rcv_load : in std_logic; -- load control signal to spi receive register
50 ss_mask_reg : in std_logic_vector(7 downto 0); -- uc slave select register, Caution! No modification, not word size
51 ss_in_int : inout std_logic; -- internal sampled version of ss_in_n needed by uc to generate an interrupt
52 xmit_empty : inout std_logic; -- flag indicating that spitr is empty
53 xmit_empty_reset : in std_logic; -- xmit empty flag reset when spitr is written
54 rcv_full : out std_logic; -- flag indicating that spirr has new data
55 rcv_full_reset : in std_logic; -- rcv full flag reset when spirr is read
56 cpha : in std_logic; -- clock phase from uc
57 cpol : in std_logic; -- clock polarity from uc
58
59 -- spi interface signals
60 ss_n : out std_logic_vector(7 downto 0); -- slave select signals Caution! NO modification slave select, not word size
61 ss_in_n : in std_logic; -- input slave select indicating master bus contention
62 ss_n_int : inout std_logic; -- internal ss_n that is masked with slave select register
63
64 -- internal interface signals
65 sck_int : in std_logic; -- internal version of sck with cpha=1
66 sck_int_re : in std_logic; -- indicates rising edge on internal sck
67 sck_int_fe : in std_logic; -- indicates falling edge on internal sck
68 sck_re : in std_logic; -- indicates rising edge on external sck
69 sck_fe : in std_logic; -- indicates falling edge on external sck
70 xmit_shift : out std_logic; -- shift control signal to spi xmit shift register
71 xmit_load : inout std_logic; -- load control signal to the spi xmit shift register
72 clk1_mask : out std_logic; -- masks cpha=1 version of sck
73 clk0_mask : out std_logic; -- masks cpha=0 version of sck
74
75 -- clock and reset
76 reset : in std_logic; -- active low reset
77 clk : in std_logic -- clock
78 );
79end spi_control_sm;
80
81architecture DEFINITION of spi_control_sm is
82
83--**************************** Constants ***************************************
84
85constant RESET_ACTIVE : std_logic := '0';
86
87constant SIXTEEN : std_logic_vector(4 downto 0) := "10000"; -- *Mod: width changed from 4 to 5 bits, Caution! bit counter
88
89--**************************** Signals ***************************************
90
91type SPI_STATE_TYPE is (IDLE, ASSERT_SSN1, ASSERT_SSN2, UNMASK_SCK, XFER_BIT,
92 ASSERT_DONE, CHK_START, MASK_SCK, HOLD_SSN1, HOLD_SSN2,
93 NEGATE_SSN);
94
95signal spi_state, next_spi_state : SPI_STATE_TYPE;
96
97signal bit_cnt : STD_LOGIC_VECTOR(4 downto 0); -- Caution! bit counter output *Mod: width changed from 4 to 5 bits
98signal bit_cnt_en : STD_LOGIC; -- count enable for bit counter
99signal bit_cnt_rst : STD_LOGIC; -- reset for bit counter from SPI control state machine
100signal bit_cnt_reset : STD_LOGIC; -- reset to bit counter that includes SS_IN_INT
101signal ss_in_neg : STD_LOGIC; -- SS_IN_N sampled with rising edge of clk
102signal ss_in_pos : STD_LOGIC; -- SS_IN_N sampled with negative edge of clk
103signal ss_n_out : STD_LOGIC_VECTOR(7 downto 0); -- output SS_N that are 3-stated if SS_IN_INT is asserted indicating another master slave select,
104 -- do not change width
105
106--**************************** Component Definitions ********************************
107-- 5-bit counter for bit counter
108component upcnt5 --*Mod: 5 instead of 4 bit counter
109 port(
110 cnt_en : in STD_LOGIC; -- Count enable
111 clr : in STD_LOGIC; -- Active high clear
112 clk : in STD_LOGIC; -- Clock
113 qout : inout STD_LOGIC_VECTOR (4 downto 0) -- *Mod: 5 instead of 4 bit counter
114 );
115end component;
116
117begin
118
119 --************************** Bit Counter Instantiation ********************************
120 BIT_CNTR : upcnt5 --*Mod: 5 instead of 4 bit counter
121 port map(
122 cnt_en => bit_cnt_en,
123 clr => bit_cnt_reset,
124 clk => sck_int,
125 qout => bit_cnt
126 );
127
128 --************************** SS_IN_N Input synchronization *******************************
129 -- When the SS_IN_N input is asserted, it indicates that there is another master on the bus
130 -- that has selected this master as a slave. When this signal asserts, the SPI master needs
131 -- to reset and tristate outputs. Therefore, the SS_IN_N input should be synchronized with the
132 -- system clock to prevent glitches on this signal from reseting the SPI master. The proces
133 -- below first samples SS_IN_N with the rising edge of the system clock and the falling edge
134 -- of the system clock. If both of these samples show that the signal is asserted, then the
135 -- internal SS_IN_INT signal will assert. SS_IN_INT is passed to the uC logic to generate an
136 -- interrupt if interrupts have been enabled. It is also passed to the SCK logic and the
137 -- SPI Xmit shift register to tri-state the SCK and MOSI outputs.
138
139 ss_in_rising: process(clk, reset)
140 begin
141 if reset = RESET_ACTIVE then
142 ss_in_pos <= '1';
143 elsif clk'event and clk = '1' then
144 ss_in_pos <= ss_in_n;
145 end if;
146 end process;
147
148 ss_in_falling: process (clk, reset)
149 begin
150 if reset = RESET_ACTIVE then
151 ss_in_neg <= '1';
152 elsif clk'event and clk = '0' then
153 ss_in_neg <= ss_in_n;
154 end if;
155 end process;
156
157 ss_in_sample: process(clk,reset)
158 begin
159 if reset = RESET_ACTIVE then
160 ss_in_int <= '1';
161 elsif clk'event and clk = '1' then
162 if ss_in_pos = '0' and ss_in_neg = '0' then
163 ss_in_int <= '0';
164 else
165 ss_in_int <= '1';
166 end if;
167 end if;
168 end process;
169
170 --************************** Bit Counter reset ***************************************
171 -- The bit counter needs to be reset when the reset signal is asserted from the SPI control
172 -- state machine is asserted and when SS_IN_INT is asserted
173 -- is asserted
174 bit_cnt_reset <= RESET_ACTIVE when bit_cnt_rst = RESET_ACTIVE or ss_in_int = '0'
175 else not(RESET_ACTIVE);
176
177 --************************** SPI Control State Machine *******************************
178 -- Register process registers next state signals
179 -- Return to IDLE state whenever SS_IN_INT is asserted
180
181 spi_sm_reg:process(clk, reset, ss_in_int)
182 begin
183 -- Set state to IDLE upon reset
184 if (reset = RESET_ACTIVE or ss_in_int = '0') then
185 spi_state <= IDLE;
186 elsif clk'event and clk = '1' then
187 spi_state <= next_spi_state;
188 end if;
189 end process;
190
191 -- Combinatorial process determines next state logic
192
193 spi_sm_comb: process(spi_state, start,bit_cnt, sck_re, sck_fe, sck_int_re, sck_int_fe,
194 xmit_empty, cpha, cpol)
195
196 begin
197
198 -- set defaults
199 clk0_mask <= '0';
200 clk1_mask <= '0';
201 bit_cnt_en <= '0';
202 bit_cnt_rst <= RESET_ACTIVE;
203 next_spi_state <= spi_state;
204 done <= '0';
205 xmit_shift <= '0';
206 xmit_load <= '0';
207
208 case spi_state is
209
210 --********************* IDLE State *****************
211 when IDLE =>
212 if start = '1' and xmit_empty = '0' then
213 next_spi_state <= ASSERT_SSN1;
214 end if;
215
216 --********************* ASSERT_SSN1 State *****************
217 when ASSERT_SSN1 =>
218 -- this state asserts SS_N and waits for first edge of SCK_INT
219 -- SS_N must be asserted ~1 SCK before SCK is output from chip
220 if sck_int_re = '1' then
221 next_spi_state <= ASSERT_SSN2;
222 end if;
223
224 --********************* ASSERT_SSN2 State *****************
225 when ASSERT_SSN2 =>
226 -- this state asserts SS_N and waits for next edge of SCK_INT
227 -- SS_N must be asserted ~1 SCK before SCK is output from chip
228 if sck_int_fe = '1' then
229 next_spi_state <= UNMASK_SCK;
230 end if;
231
232 --********************* UNMASK_SCK State *****************
233 when UNMASK_SCK =>
234 bit_cnt_rst <= not(RESET_ACTIVE); -- release bit counter from reset
235 bit_cnt_en <= '1'; -- enable bit counter
236 clk1_mask <= '1'; -- unmask sck_1
237 xmit_load <= '1'; -- load SPI shift register
238
239 if sck_int_re = '1' then
240 -- first rising edge of CPHA=1 clock with SS_N asserted
241 -- transition to XFER_BIT state and unmask CPHA=0 clk
242 next_spi_state <= XFER_BIT;
243 end if;
244
245 --********************* XFER_BIT State *****************
246 when XFER_BIT =>
247 clk0_mask <= '1'; -- unmask CPHA=0 clock
248 clk1_mask <= '1'; -- unmask CPHA=1 clock
249 bit_cnt_en <= '1'; -- enable bit counter
250 bit_cnt_rst <= not(RESET_ACTIVE); -- release bit counter from reset
251
252 xmit_shift <= '1'; -- enable shifting of SPI shift registers
253
254 if bit_cnt = SIXTEEN then -- *Mod: SIXTEEN instead of EIGHT bit
255 -- all 16 bits have transferred
256 next_spi_state <= ASSERT_DONE;
257 end if;
258
259 --********************* ASSERT_DONE State *****************
260 when ASSERT_DONE =>
261 -- this state asserts done to the uC so that new data
262 -- can be written into the transmit register or data
263 -- can be read from the receive register
264 done <= '1';
265 clk0_mask <= '1';
266 clk1_mask <= '1';
267 xmit_shift <= '1';
268 if sck_int_fe = '1' then
269 next_spi_state <= CHK_START;
270 end if;
271
272 --********************* CHK_START State *****************
273 when CHK_START =>
274 clk0_mask <= '1';
275 clk1_mask <= '1';
276 done <= '1';
277 bit_cnt_en <= '1';
278 bit_cnt_rst <= not(RESET_ACTIVE); -- release bit counter from reset
279 if cpha = '0' then
280 -- when CPHA = 0, have to negate slave select and then
281 -- re-assert it. Need to wait for last SCK pulse to complete
282 -- and mask SCK before negating SS_N.
283 if (sck_re = '1' and cpol = '1') or (sck_fe = '1' and cpol = '0') then
284 clk0_mask <= '0';
285 clk1_mask <= '0';
286 next_spi_state <= MASK_SCK;
287 end if;
288 elsif start = '1' and xmit_empty = '0' then
289 -- CPHA=1 and have more data to transfer, go back to
290 -- UNMASK_CK state
291 clk1_mask <= '1';
292 xmit_load <= '1'; -- load SPI shift register
293 next_spi_state <= UNMASK_SCK;
294 else
295 -- CPHA=1 and no more data to transfer
296 -- wait for last SCKs and then mask SCK
297 if (sck_re = '1' and cpol = '1') or (sck_fe = '1' and cpol = '0') then
298 clk0_mask <= '0';
299 clk1_mask <= '0';
300 next_spi_state <= MASK_SCK;
301 end if;
302 clk0_mask <= '0';
303 clk1_mask <= '1';
304 end if;
305
306 --********************* MASK_SCK State *****************
307 when MASK_SCK =>
308 done <= '1';
309 -- wait for next internal SCK edge
310 -- to help provide SS_N hold time
311 if sck_int_fe <= '1' then
312 next_spi_state <= HOLD_SSN1;
313 end if;
314
315 --********************* HOLD_SSN1 State *****************
316 when HOLD_SSN1 =>
317 -- This state waits for another SCK edge
318 -- to provide SS_N hold time
319 if sck_int_fe = '1' then
320 next_spi_state <= HOLD_SSN2;
321 end if;
322
323 --********************* HOLD_SSN2 State *****************
324 when HOLD_SSN2 =>
325 -- This state waits for another SCK edge
326 -- to provide SS_N hold time
327 if sck_int_fe = '1' then
328 next_spi_state <= NEGATE_SSN;
329 end if;
330
331 --********************* NEGATE_SSN State *****************
332 when NEGATE_SSN =>
333 -- SS_N should negate for an entire SCK
334 -- This state waits for an SCK edge
335 if sck_int_fe = '1' then
336 next_spi_state <= IDLE;
337 end if;
338
339 --********************* Default State *****************
340 when others =>
341 next_spi_state <= IDLE;
342 end case;
343 end process;
344
345 -- assert slave select when spi_state machine is in any state but IDLE or NEGATE_SSN
346 ss_n_int <= '1' when (spi_state = IDLE or spi_state = NEGATE_SSN) else '0';
347
348 --xmit_load <= '1' when (spi_state = UNMASK_SCK) else '0';
349
350
351 --************************** Register Full/Empty flags *******************************
352 -- When data is loaded into the SPI transmit shift register from SPITR, the XMIT_EMPTY
353 -- flag is set, indicating to the uC that new data can be written into SPITR. Note that
354 -- the SPI transmit shift register is clocked from SCK, therefore, this flag is clocked
355 -- from SCK.
356 mt_flag_process: process (sck_int, xmit_empty_reset, reset)
357 begin
358 if xmit_empty_reset = RESET_ACTIVE or reset = RESET_ACTIVE then
359 xmit_empty <= '0';
360 elsif sck_int'event and sck_int = '1' then
361 if xmit_empty_reset = RESET_ACTIVE then
362 -- reset empty flag because uC has written data to SPITR
363 xmit_empty <= '0';
364 elsif xmit_load = '1' then
365 -- set empty flag because SPITR data has been loaded into
366 -- SPI transmit shift register
367 xmit_empty <= '1';
368 end if;
369 end if;
370 end process;
371
372 -- When data is loaded into SPIRR, the RCV_FULL flag is set, indicating to the uC that
373 -- new data from the SPI bus has been received.
374 full_flag_process: process (reset, clk)
375 begin
376 if reset = RESET_ACTIVE then
377 rcv_full <= '0';
378 elsif clk'event and clk = '1' then
379 if rcv_full_reset = RESET_ACTIVE then
380 -- reset the full flag because the spirr has been read
381 rcv_full <= '0';
382 elsif rcv_load = '1' then
383 -- set the full flag because data has been loaded in spirr
384 rcv_full <= '1';
385 end if;
386 end if;
387 end process;
388
389 --************************** Slave Selects *******************************
390 -- The internal slave select signal generated by the SPI Control state machine
391 -- is masked by the uC slave select register. The SS_N outputs are clocked on the
392 -- falling edge of the system clock.
393 ss_n_process: process ( reset, clk)
394 variable i : integer;
395
396 begin
397 if reset = RESET_ACTIVE then
398 ss_n_out <= (others => '1');
399 elsif clk'event and clk = '0' then
400 for i in 0 to 7 loop
401 if ss_n_int = '0' and ss_mask_reg (i) = '1' then
402 ss_n_out(i) <= '0'; -- assert corresponding slave select
403 else
404 ss_n_out(i) <= '1';
405 end if;
406 end loop;
407 end if;
408 end process;
409
410 -- Slave selects are 3-stated if SS_IN_INT is asserted
411 ss_n <= ss_n_out when ss_in_int = '1'
412 else (others => 'Z');
413
414end DEFINITION;
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