source: firmware/FTU/old_design/spi_interface/spi_interface_16.vhd@ 16318

Last change on this file since 16318 was 156, checked in by qweitzel, 16 years ago
First check-in of VHDL code for FTU: counters, dcm, spi
File size: 9.1 KB
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1---------------------------------------------------------------------------------------------
2---------------------------------------------------------------------------------------------
3-- File: spi_interface_16.vhd
4--
5--
6-- Original file: spi_interface.vhd
7--
8-- Created: 12-12-02 JRH
9-- This file contains the interconnect structure of the SPI interface portion of
10-- the SPI Master design. It was originally created in schematic form, but was
11-- converted to VHDL from the VHF file generated by the ECS tool.
12--
13---------------------------------------------------------------------------------------------
14---------------------------------------------------------------------------------------------
15-- Modified from 8 to 16 bit word size by Patrick Vogler
16-- 18th November 2009
17--
18-- Modifications are marked by: *Mod: <modification>
19--
20-- Cleaned up by Quirin Weitzel
21-- 20th January 2010
22---------------------------------------------------------------------------------------------
23---------------------------------------------------------------------------------------------
24library IEEE;
25library UNISIM;
26use IEEE.STD_LOGIC_1164.ALL;
27use IEEE.NUMERIC_STD.ALL;
28use UNISIM.Vcomponents.ALL;
29
30entity spi_interface_16 is
31 port(
32 clk : IN STD_LOGIC;
33 clkdiv : IN STD_LOGIC_VECTOR (1 downto 0);
34 cpha : IN STD_LOGIC;
35 cpol : IN STD_LOGIC;
36 miso : IN STD_LOGIC;
37 rcv_cpol : IN STD_LOGIC;
38 rcv_full_reset : IN STD_LOGIC;
39 reset : IN STD_LOGIC;
40 ss_in_n : IN STD_LOGIC;
41 ss_mask_reg : IN STD_LOGIC_VECTOR (7 downto 0);-- slave select signals, caution! NO modification, slave select, not word size
42 start : IN STD_LOGIC;
43 xmit_data : IN STD_LOGIC_VECTOR (15 downto 0);-- *Mod: 15 instead of 7, transmit data word extended from 8 to 16 bit
44 xmit_empty_reset : IN STD_LOGIC;
45 done : OUT STD_LOGIC;
46 mosi : OUT STD_LOGIC;
47 rcv_data : OUT STD_LOGIC_VECTOR (15 downto 0);-- *Mod: 15 instead of 7, recieve data word extended from 8 to 16 bit
48 rcv_full : OUT STD_LOGIC;
49 ss_n : OUT STD_LOGIC_VECTOR (7 downto 0);-- slave select signals, caution! NO modification, slave select, not word size
50 rcv_load : INOUT STD_LOGIC;
51 sck : INOUT STD_LOGIC;
52 ss_in_int : INOUT STD_LOGIC;
53 ss_n_int : INOUT STD_LOGIC;
54 xmit_empty : INOUT STD_LOGIC
55 );
56end spi_interface_16;
57
58ARCHITECTURE SCHEMATIC OF spi_interface_16 IS
59
60 SIGNAL clk0_mask : STD_LOGIC;
61 SIGNAL clk1_mask : STD_LOGIC;
62 SIGNAL sck_1 : STD_LOGIC;
63 SIGNAL sck_fe : STD_LOGIC;
64 SIGNAL sck_int_fe : STD_LOGIC;
65 SIGNAL sck_int_re : STD_LOGIC;
66 SIGNAL sck_re : STD_LOGIC;
67 SIGNAL vcc : STD_LOGIC;
68 SIGNAL xmit_load : STD_LOGIC;
69 SIGNAL xmit_shift : STD_LOGIC;
70
71 ATTRIBUTE fpga_dont_touch : STRING;
72 ATTRIBUTE fpga_dont_touch OF XLXI_9 : LABEL IS "true";
73
74 COMPONENT sck_logic
75 PORT(
76 clk : IN STD_LOGIC;
77 clk0_mask : IN STD_LOGIC;
78 clk1_mask : IN STD_LOGIC;
79 clkdiv : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
80 cpha : IN STD_LOGIC;
81 cpol : IN STD_LOGIC;
82 reset : IN STD_LOGIC;
83 ss_in_int : IN STD_LOGIC;
84 sck : INOUT STD_LOGIC;
85 sck_1 : INOUT STD_LOGIC;
86 sck_fe : OUT STD_LOGIC;
87 sck_int_fe : OUT STD_LOGIC;
88 sck_int_re : OUT STD_LOGIC;
89 sck_re : OUT STD_LOGIC
90 );
91 END COMPONENT;
92
93 COMPONENT spi_control_sm
94 PORT(
95 clk : IN STD_LOGIC;
96 cpha : IN STD_LOGIC;
97 cpol : IN STD_LOGIC;
98 rcv_full_reset : IN STD_LOGIC;
99 rcv_load : IN STD_LOGIC;
100 reset : IN STD_LOGIC;
101 sck_fe : IN STD_LOGIC;
102 sck_int : IN STD_LOGIC;
103 sck_int_fe : IN STD_LOGIC;
104 sck_int_re : IN STD_LOGIC;
105 sck_re : IN STD_LOGIC;
106 ss_in_n : IN STD_LOGIC;
107 ss_mask_reg : IN STD_LOGIC_VECTOR (7 DOWNTO 0);-- slave select signals, caution, NO modification, slave select, not word size
108 start : IN STD_LOGIC;
109 xmit_empty_reset : IN STD_LOGIC;
110 ss_in_int : INOUT STD_LOGIC;
111 ss_n_int : INOUT STD_LOGIC;
112 xmit_empty : INOUT STD_LOGIC;
113 xmit_load : INOUT STD_LOGIC;
114 clk0_mask : OUT STD_LOGIC;
115 clk1_mask : OUT STD_LOGIC;
116 done : OUT STD_LOGIC;
117 rcv_full : OUT STD_LOGIC;
118 ss_n : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- slave select signals, caution! NO modification slave select, not word size
119 xmit_shift : OUT STD_LOGIC
120 );
121 END COMPONENT;
122
123 COMPONENT spi_rcv_shift_reg
124 PORT(
125 cpol : IN STD_LOGIC;
126 miso : IN STD_LOGIC;
127 rcv_cpol : IN STD_LOGIC;
128 reset : IN STD_LOGIC;
129 sck_fe : IN STD_LOGIC;
130 sck_re : IN STD_LOGIC;
131 sclk : IN STD_LOGIC;
132 shift_en : IN STD_LOGIC;
133 ss_in_int : IN STD_LOGIC;
134 data_out : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);-- *Mod: 15 instead of 7, recieve data word extended from 8 to 16 bit
135 rcv_load : OUT STD_LOGIC
136 );
137 END COMPONENT;
138
139 COMPONENT spi_xmit_shift_reg
140 PORT(
141 data_in : IN STD_LOGIC_VECTOR (15 DOWNTO 0);-- *Mod: 15 instead of 7, transmit data word extended from 8 to 16 bit
142 data_ld : IN STD_LOGIC;
143 reset : IN STD_LOGIC;
144 sclk : IN STD_LOGIC;
145 shift_en : IN STD_LOGIC;
146 shift_in : IN STD_LOGIC;
147 ss_in_int : IN STD_LOGIC;
148 sys_clk : IN STD_LOGIC;
149 mosi : OUT STD_LOGIC
150 );
151 END COMPONENT;
152
153BEGIN
154
155 XLXI_9 : NAND2B1
156 PORT MAP(
157 I0=>xmit_shift, I1=>xmit_shift, O=>vcc
158 );
159
160 SCK_GEN : sck_logic
161 PORT MAP(
162 clk=>clk, clk0_mask=>clk0_mask, clk1_mask=>clk1_mask,
163 clkdiv(1)=>clkdiv(1), clkdiv(0)=>clkdiv(0), cpha=>cpha, cpol=>cpol,
164 reset=>reset, ss_in_int=>ss_in_int, sck=>sck, sck_1=>sck_1,
165 sck_fe=>sck_fe, sck_int_fe=>sck_int_fe, sck_int_re=>sck_int_re,
166 sck_re=>sck_re
167 );
168
169 spi_ctrl_sm : spi_control_sm
170 PORT MAP(
171 clk=>clk, cpha=>cpha, cpol=>cpol,
172 rcv_full_reset=>rcv_full_reset, rcv_load=>rcv_load, reset=>reset,
173 sck_fe=>sck_fe, sck_int=>sck_1, sck_int_fe=>sck_int_fe,
174 sck_int_re=>sck_int_re, sck_re=>sck_re, ss_in_n=>ss_in_n,
175 ss_mask_reg(7)=>ss_mask_reg(7), ss_mask_reg(6)=>ss_mask_reg(6),
176 ss_mask_reg(5)=>ss_mask_reg(5), ss_mask_reg(4)=>ss_mask_reg(4),
177 ss_mask_reg(3)=>ss_mask_reg(3), ss_mask_reg(2)=>ss_mask_reg(2),
178 ss_mask_reg(1)=>ss_mask_reg(1), ss_mask_reg(0)=>ss_mask_reg(0),
179 start=>start, xmit_empty_reset=>xmit_empty_reset, ss_in_int=>ss_in_int,
180 ss_n_int=>ss_n_int, xmit_empty=>xmit_empty, xmit_load=>xmit_load,
181 clk0_mask=>clk0_mask, clk1_mask=>clk1_mask, done=>done,
182 rcv_full=>rcv_full, ss_n(7)=>ss_n(7), ss_n(6)=>ss_n(6), ss_n(5)=>ss_n(5),
183 ss_n(4)=>ss_n(4), ss_n(3)=>ss_n(3), ss_n(2)=>ss_n(2), ss_n(1)=>ss_n(1),
184 ss_n(0)=>ss_n(0), xmit_shift=>xmit_shift
185 );
186
187--------------------------------------------------------------------------
188-- *Mod: recieve data word extended from 8 to 16 bit in this block ------
189 rcv_shift_reg : spi_rcv_shift_reg
190 PORT MAP(
191 cpol=>cpol, miso=>miso, rcv_cpol=>rcv_cpol, reset=>reset,
192 sck_fe=>sck_fe, sck_re=>sck_re, sclk=>sck, shift_en=>ss_n_int,
193 ss_in_int=>ss_in_int,
194 data_out(15)=>rcv_data(15), data_out(14)=>rcv_data(14),
195 data_out(13)=>rcv_data(13), data_out(12)=>rcv_data(12),
196 data_out(11)=>rcv_data(11), data_out(10)=>rcv_data(10),
197 data_out(9)=>rcv_data(9), data_out(8)=>rcv_data(8),
198 data_out(7)=>rcv_data(7), data_out(6)=>rcv_data(6),
199 data_out(5)=>rcv_data(5), data_out(4)=>rcv_data(4),
200 data_out(3)=>rcv_data(3), data_out(2)=>rcv_data(2),
201 data_out(1)=>rcv_data(1), data_out(0)=>rcv_data(0),
202 rcv_load=>rcv_load
203 );
204-- *Mod: recieve data word extended from 8 to 16 bit in this block -----
205-------------------------------------------------------------------------
206
207--------------------------------------------------------------------------
208-- *Mod: transmit data word extended from 8 to 16 bit in this block -----
209 xmit_shift_reg : spi_xmit_shift_reg
210 PORT MAP(
211 data_in(15)=>xmit_data(15), data_in(14)=>xmit_data(14),
212 data_in(13)=>xmit_data(13), data_in(12)=>xmit_data(12),
213 data_in(11)=>xmit_data(11), data_in(10)=>xmit_data(10),
214 data_in(9)=>xmit_data(9), data_in(8)=>xmit_data(8),
215 data_in(7)=>xmit_data(7), data_in(6)=>xmit_data(6),
216 data_in(5)=>xmit_data(5), data_in(4)=>xmit_data(4),
217 data_in(3)=>xmit_data(3), data_in(2)=>xmit_data(2),
218 data_in(1)=>xmit_data(1), data_in(0)=>xmit_data(0),
219 data_ld=>xmit_load,
220 reset=>reset, sclk=>sck_1, shift_en=>xmit_shift, shift_in=>vcc,
221 ss_in_int=>ss_in_int, sys_clk=>clk, mosi=>mosi
222 );
223-- *Mod: transmit data word extended from 8 to 16 bit in this block -----
224--------------------------------------------------------------------------
225
226END SCHEMATIC;
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