source: firmware/FTU/ram/FTU_dual_port_ram.vhd@ 16318

Last change on this file since 16318 was 273, checked in by qweitzel, 15 years ago
new structure for FTU firmware, not yet finished
File size: 5.6 KB
Line 
1--------------------------------------------------------------------------------
2-- This file is owned and controlled by Xilinx and must be used --
3-- solely for design, simulation, implementation and creation of --
4-- design files limited to Xilinx devices or technologies. Use --
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6-- and immediately terminates your license. --
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8-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
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11-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
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16-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
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18-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
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20-- FOR A PARTICULAR PURPOSE. --
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22-- Xilinx products are not intended for use in life support --
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25-- --
26-- (c) Copyright 1995-2009 Xilinx, Inc. --
27-- All rights reserved. --
28--------------------------------------------------------------------------------
29-- You must compile the wrapper file FTU_dual_port_ram.vhd when simulating
30-- the core, FTU_dual_port_ram. When compiling the wrapper file, be sure to
31-- reference the XilinxCoreLib VHDL simulation library. For detailed
32-- instructions, please refer to the "CORE Generator Help".
33
34-- The synthesis directives "translate_off/translate_on" specified
35-- below are supported by Xilinx, Mentor Graphics and Synplicity
36-- synthesis tools. Ensure they are correct for your synthesis tool(s).
37
38LIBRARY ieee;
39USE ieee.std_logic_1164.ALL;
40-- synthesis translate_off
41Library XilinxCoreLib;
42-- synthesis translate_on
43ENTITY FTU_dual_port_ram IS
44 port (
45 clka: IN std_logic;
46 ena: IN std_logic;
47 wea: IN std_logic_VECTOR(0 downto 0);
48 addra: IN std_logic_VECTOR(4 downto 0);
49 dina: IN std_logic_VECTOR(7 downto 0);
50 douta: OUT std_logic_VECTOR(7 downto 0);
51 clkb: IN std_logic;
52 enb: IN std_logic;
53 web: IN std_logic_VECTOR(0 downto 0);
54 addrb: IN std_logic_VECTOR(3 downto 0);
55 dinb: IN std_logic_VECTOR(15 downto 0);
56 doutb: OUT std_logic_VECTOR(15 downto 0));
57END FTU_dual_port_ram;
58
59ARCHITECTURE FTU_dual_port_ram_a OF FTU_dual_port_ram IS
60-- synthesis translate_off
61component wrapped_FTU_dual_port_ram
62 port (
63 clka: IN std_logic;
64 ena: IN std_logic;
65 wea: IN std_logic_VECTOR(0 downto 0);
66 addra: IN std_logic_VECTOR(4 downto 0);
67 dina: IN std_logic_VECTOR(7 downto 0);
68 douta: OUT std_logic_VECTOR(7 downto 0);
69 clkb: IN std_logic;
70 enb: IN std_logic;
71 web: IN std_logic_VECTOR(0 downto 0);
72 addrb: IN std_logic_VECTOR(3 downto 0);
73 dinb: IN std_logic_VECTOR(15 downto 0);
74 doutb: OUT std_logic_VECTOR(15 downto 0));
75end component;
76
77-- Configuration specification
78 for all : wrapped_FTU_dual_port_ram use entity XilinxCoreLib.blk_mem_gen_v3_3(behavioral)
79 generic map(
80 c_has_regceb => 0,
81 c_has_regcea => 0,
82 c_mem_type => 2,
83 c_rstram_b => 0,
84 c_rstram_a => 0,
85 c_has_injecterr => 0,
86 c_rst_type => "SYNC",
87 c_prim_type => 1,
88 c_read_width_b => 16,
89 c_initb_val => "0",
90 c_family => "spartan3",
91 c_read_width_a => 8,
92 c_disable_warn_bhv_coll => 0,
93 c_write_mode_b => "NO_CHANGE",
94 c_init_file_name => "no_coe_file_loaded",
95 c_write_mode_a => "NO_CHANGE",
96 c_mux_pipeline_stages => 0,
97 c_has_mem_output_regs_b => 0,
98 c_has_mem_output_regs_a => 0,
99 c_load_init_file => 0,
100 c_xdevicefamily => "spartan3a",
101 c_write_depth_b => 16,
102 c_write_depth_a => 32,
103 c_has_rstb => 0,
104 c_has_rsta => 0,
105 c_has_mux_output_regs_b => 0,
106 c_inita_val => "0",
107 c_has_mux_output_regs_a => 0,
108 c_addra_width => 5,
109 c_addrb_width => 4,
110 c_default_data => "0",
111 c_use_ecc => 0,
112 c_algorithm => 2,
113 c_disable_warn_bhv_range => 0,
114 c_write_width_b => 16,
115 c_write_width_a => 8,
116 c_read_depth_b => 16,
117 c_read_depth_a => 32,
118 c_byte_size => 9,
119 c_sim_collision_check => "ALL",
120 c_common_clk => 0,
121 c_wea_width => 1,
122 c_has_enb => 1,
123 c_web_width => 1,
124 c_has_ena => 1,
125 c_use_byte_web => 0,
126 c_use_byte_wea => 0,
127 c_rst_priority_b => "CE",
128 c_rst_priority_a => "CE",
129 c_use_default_data => 0);
130-- synthesis translate_on
131BEGIN
132-- synthesis translate_off
133U0 : wrapped_FTU_dual_port_ram
134 port map (
135 clka => clka,
136 ena => ena,
137 wea => wea,
138 addra => addra,
139 dina => dina,
140 douta => douta,
141 clkb => clkb,
142 enb => enb,
143 web => web,
144 addrb => addrb,
145 dinb => dinb,
146 doutb => doutb);
147-- synthesis translate_on
148
149END FTU_dual_port_ram_a;
150
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