| 1 | --------------------------------------------------------------------------------
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| 2 | -- This file is owned and controlled by Xilinx and must be used --
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| 3 | -- solely for design, simulation, implementation and creation of --
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| 4 | -- design files limited to Xilinx devices or technologies. Use --
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| 5 | -- with non-Xilinx devices or technologies is expressly prohibited --
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| 6 | -- and immediately terminates your license. --
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| 7 | -- --
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| 8 | -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
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| 9 | -- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
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| 10 | -- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
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| 11 | -- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
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| 12 | -- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
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| 13 | -- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
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| 14 | -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
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| 15 | -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
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| 16 | -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
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| 17 | -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
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| 18 | -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
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| 19 | -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
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| 20 | -- FOR A PARTICULAR PURPOSE. --
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| 21 | -- --
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| 22 | -- Xilinx products are not intended for use in life support --
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| 23 | -- appliances, devices, or systems. Use in such applications are --
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| 24 | -- expressly prohibited. --
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| 25 | -- --
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| 26 | -- (c) Copyright 1995-2009 Xilinx, Inc. --
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| 27 | -- All rights reserved. --
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| 28 | --------------------------------------------------------------------------------
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| 29 | -- The following code must appear in the VHDL architecture header:
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| 30 |
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| 31 | ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
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| 32 | component FTU_dual_port_ram
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| 33 | port (
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| 34 | clka: IN std_logic;
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| 35 | ena: IN std_logic;
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| 36 | wea: IN std_logic_VECTOR(0 downto 0);
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| 37 | addra: IN std_logic_VECTOR(4 downto 0);
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| 38 | dina: IN std_logic_VECTOR(7 downto 0);
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| 39 | douta: OUT std_logic_VECTOR(7 downto 0);
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| 40 | clkb: IN std_logic;
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| 41 | enb: IN std_logic;
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| 42 | web: IN std_logic_VECTOR(0 downto 0);
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| 43 | addrb: IN std_logic_VECTOR(3 downto 0);
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| 44 | dinb: IN std_logic_VECTOR(15 downto 0);
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| 45 | doutb: OUT std_logic_VECTOR(15 downto 0));
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| 46 | end component;
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| 47 |
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| 48 | -- Synplicity black box declaration
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| 49 | attribute syn_black_box : boolean;
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| 50 | attribute syn_black_box of FTU_dual_port_ram: component is true;
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| 51 |
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| 52 | -- COMP_TAG_END ------ End COMPONENT Declaration ------------
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| 53 |
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| 54 | -- The following code must appear in the VHDL architecture
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| 55 | -- body. Substitute your own instance name and net names.
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| 56 |
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| 57 | ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
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| 58 | your_instance_name : FTU_dual_port_ram
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| 59 | port map (
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| 60 | clka => clka,
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| 61 | ena => ena,
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| 62 | wea => wea,
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| 63 | addra => addra,
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| 64 | dina => dina,
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| 65 | douta => douta,
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| 66 | clkb => clkb,
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| 67 | enb => enb,
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| 68 | web => web,
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| 69 | addrb => addrb,
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| 70 | dinb => dinb,
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| 71 | doutb => doutb);
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| 72 | -- INST_TAG_END ------ End INSTANTIATION Template ------------
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| 73 |
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| 74 | -- You must compile the wrapper file FTU_dual_port_ram.vhd when simulating
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| 75 | -- the core, FTU_dual_port_ram. When compiling the wrapper file, be sure to
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| 76 | -- reference the XilinxCoreLib VHDL simulation library. For detailed
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| 77 | -- instructions, please refer to the "CORE Generator Help".
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| 78 |
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